Equations

********** Mapped Logic **********

Mmult_bin_deg_mult0000_Mxor__index0014 <= ((u2/cnt_catch_cmp_le0000 AND rx_out(4) AND NOT N_PZ_621)
      OR (u2/cnt_catch_cmp_le0000 AND NOT rx_out(4) AND N_PZ_621)
      OR (u2/cnt_catch_cmp_le0000 AND NOT rx_out(4) AND rx_out(1) AND
      NOT N_PZ_689)
      OR (rx_out(6) AND NOT rx_out(7) AND NOT rx_out(4) AND N_PZ_689)
      OR (NOT rx_out(6) AND rx_out(7) AND rx_out(3) AND NOT rx_out(4))
      OR (NOT rx_out(6) AND NOT rx_out(7) AND rx_out(3) AND rx_out(4))
      OR (rx_out(7) AND NOT rx_out(3) AND rx_out(4) AND NOT N_PZ_619)
      OR (rx_out(7) AND NOT rx_out(4) AND NOT rx_out(5) AND N_PZ_619)
      OR (rx_out(7) AND NOT rx_out(4) AND rx_out(0) AND N_PZ_619)
      OR (NOT rx_out(7) AND NOT rx_out(3) AND NOT rx_out(4) AND NOT N_PZ_619)
      OR (NOT rx_out(7) AND rx_out(4) AND NOT N_PZ_689 AND N_PZ_621)
      OR (rx_out(6) AND NOT rx_out(7) AND NOT rx_out(4) AND NOT rx_out(1) AND
      NOT N_PZ_621)
      OR (rx_out(7) AND NOT rx_out(3) AND rx_out(4) AND NOT rx_out(1) AND
      NOT N_PZ_621)
      OR (NOT rx_out(7) AND rx_out(4) AND rx_out(0) AND rx_out(1) AND
      N_PZ_619)
      OR (rx_out(7) AND NOT rx_out(0) AND rx_out(1) AND NOT N_PZ_689 AND
      N_PZ_619 AND NOT N_PZ_621)
      OR (NOT rx_out(7) AND NOT rx_out(3) AND NOT rx_out(4) AND rx_out(5) AND
      NOT rx_out(0) AND NOT rx_out(1)));

Mmult_bin_deg_mult0000_Mxor__index0015 <= ((rx_out(6) AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0016)
      OR (rx_out(7) AND NOT rx_out(5) AND
      Mmult_bin_deg_mult0000_Mxor__index0014)
      OR (NOT rx_out(7) AND rx_out(4) AND rx_out(5))
      OR (NOT rx_out(7) AND rx_out(3) AND rx_out(5) AND N_PZ_907)
      OR (NOT rx_out(7) AND rx_out(5) AND rx_out(0) AND N_PZ_619)
      OR (NOT rx_out(7) AND rx_out(5) AND rx_out(1) AND N_PZ_619)
      OR (rx_out(3) AND rx_out(5) AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0016 AND NOT N_PZ_907)
      OR (NOT rx_out(7) AND rx_out(3) AND rx_out(2) AND rx_out(1) AND
      NOT N_PZ_621)
      OR (NOT rx_out(7) AND rx_out(4) AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0014 AND N_PZ_689 AND N_PZ_619)
      OR (NOT rx_out(7) AND rx_out(4) AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0014 AND NOT N_PZ_689 AND N_PZ_621)
      OR (rx_out(4) AND rx_out(5) AND rx_out(0) AND rx_out(1) AND
      N_PZ_619)
      OR (NOT rx_out(7) AND rx_out(4) AND rx_out(0) AND rx_out(1) AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0014 AND N_PZ_619));

Mmult_bin_deg_mult0000_Mxor__index0016 <= rx_out(6)
      XOR ((rx_out(7) AND NOT rx_out(5) AND
      Mmult_bin_deg_mult0000_Mxor__index0014)
      OR (rx_out(6) AND NOT rx_out(4) AND NOT rx_out(5) AND
      Mmult_bin_deg_mult0000_Mxor__index0014)
      OR (rx_out(6) AND rx_out(7) AND NOT rx_out(3) AND NOT rx_out(4) AND
      NOT rx_out(5))
      OR (rx_out(6) AND NOT rx_out(3) AND NOT rx_out(5) AND NOT rx_out(2) AND
      Mmult_bin_deg_mult0000_Mxor__index0014)
      OR (rx_out(6) AND NOT rx_out(3) AND NOT rx_out(5) AND NOT rx_out(1) AND
      Mmult_bin_deg_mult0000_Mxor__index0014)
      OR (rx_out(6) AND rx_out(7) AND NOT rx_out(4) AND NOT rx_out(5) AND
      NOT rx_out(2) AND NOT rx_out(1)));

Mmult_bin_deg_mult0000_Mxor__index0020 <= rx_out(2)
      XOR ((Mmult_bin_deg_mult0000_Mxor__index0014 AND
      NOT Mmult_bin_deg_mult0000__or0014)
      OR (NOT Mmult_bin_deg_mult0000_Mxor__index0014 AND
      Mmult_bin_deg_mult0000__or0014));

Mmult_bin_deg_mult0000_Mxor__index0021 <= ((rx_out(3) AND rx_out(2) AND
      Mmult_bin_deg_mult0000__or0014 AND Mmult_bin_deg_mult0000_Mxor__index0015)
      OR (rx_out(3) AND NOT rx_out(2) AND
      Mmult_bin_deg_mult0000_Mxor__index0020 AND NOT Mmult_bin_deg_mult0000_Mxor__index0015)
      OR (rx_out(3) AND
      Mmult_bin_deg_mult0000_Mxor__index0014 AND NOT Mmult_bin_deg_mult0000_Mxor__index0020 AND
      Mmult_bin_deg_mult0000_Mxor__index0015)
      OR (rx_out(3) AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0014 AND NOT Mmult_bin_deg_mult0000__or0014 AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0015)
      OR (NOT rx_out(3) AND rx_out(2) AND
      Mmult_bin_deg_mult0000__or0014 AND NOT Mmult_bin_deg_mult0000_Mxor__index0015)
      OR (NOT rx_out(3) AND NOT rx_out(2) AND
      Mmult_bin_deg_mult0000_Mxor__index0020 AND Mmult_bin_deg_mult0000_Mxor__index0015)
      OR (NOT rx_out(3) AND
      Mmult_bin_deg_mult0000_Mxor__index0014 AND NOT Mmult_bin_deg_mult0000_Mxor__index0020 AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0015)
      OR (NOT rx_out(3) AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0014 AND NOT Mmult_bin_deg_mult0000__or0014 AND
      Mmult_bin_deg_mult0000_Mxor__index0015));

Mmult_bin_deg_mult0000_Mxor__index0022 <= ((rx_out(3) AND
      Mmult_bin_deg_mult0000_Mxor__index0015 AND N_PZ_907)
      OR (NOT rx_out(3) AND NOT N_PZ_907 AND
      Mmult_bin_deg_mult0000_Mxor__index0021)
      OR (rx_out(2) AND Mmult_bin_deg_mult0000__or0014 AND
      N_PZ_907 AND NOT Mmult_bin_deg_mult0000_Mxor__index0021)
      OR (NOT rx_out(2) AND
      Mmult_bin_deg_mult0000_Mxor__index0020 AND NOT Mmult_bin_deg_mult0000_Mxor__index0015 AND NOT N_PZ_907)
      OR (Mmult_bin_deg_mult0000_Mxor__index0014 AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0020 AND N_PZ_907 AND NOT Mmult_bin_deg_mult0000_Mxor__index0021)
      OR (NOT Mmult_bin_deg_mult0000_Mxor__index0014 AND
      NOT Mmult_bin_deg_mult0000__or0014 AND NOT Mmult_bin_deg_mult0000_Mxor__index0015 AND NOT N_PZ_907));

Mmult_bin_deg_mult0000_Mxor__index0029 <= rx_out(2)
XOR ((Mmult_bin_deg_mult0000_Mxor__index0021 AND NOT N_PZ_929)
OR (NOT Mmult_bin_deg_mult0000_Mxor__index0021 AND N_PZ_929));

Mmult_bin_deg_mult0000_Mxor__index0030 <= ((rx_out(3) AND rx_out(2) AND
      Mmult_bin_deg_mult0000_Mxor__index0022 AND N_PZ_929)
      OR (rx_out(3) AND NOT rx_out(2) AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0022 AND Mmult_bin_deg_mult0000_Mxor__index0029)
      OR (rx_out(3) AND
      Mmult_bin_deg_mult0000_Mxor__index0021 AND Mmult_bin_deg_mult0000_Mxor__index0022 AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0029)
      OR (rx_out(3) AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0021 AND NOT Mmult_bin_deg_mult0000_Mxor__index0022 AND NOT N_PZ_929)
      OR (NOT rx_out(3) AND rx_out(2) AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0022 AND N_PZ_929)
      OR (NOT rx_out(3) AND NOT rx_out(2) AND
      Mmult_bin_deg_mult0000_Mxor__index0022 AND Mmult_bin_deg_mult0000_Mxor__index0029)
      OR (NOT rx_out(3) AND
      Mmult_bin_deg_mult0000_Mxor__index0021 AND NOT Mmult_bin_deg_mult0000_Mxor__index0022 AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0029)
      OR (NOT rx_out(3) AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0021 AND Mmult_bin_deg_mult0000_Mxor__index0022 AND NOT N_PZ_929));

Mmult_bin_deg_mult0000_Mxor__index0031 <= N_PZ_632
      XOR ((rx_out(7) AND rx_out(5))
      OR (NOT rx_out(7) AND NOT rx_out(5))
      OR (NOT rx_out(6) AND rx_out(7) AND
      Mmult_bin_deg_mult0000_Mxor__index0014));

Mmult_bin_deg_mult0000_Mxor__index0032 <= ((rx_out(7) AND rx_out(5) AND
      Mmult_bin_deg_mult0000_Mxor__index0033)
      OR (NOT rx_out(7) AND NOT rx_out(5) AND
      Mmult_bin_deg_mult0000_Mxor__index0033)
      OR (rx_out(6) AND NOT rx_out(5) AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0033 AND N_PZ_911)
      OR (rx_out(6) AND NOT Mmult_bin_deg_mult0000__or0017 AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0033 AND N_PZ_911)
      OR (NOT rx_out(6) AND rx_out(7) AND NOT N_PZ_615 AND NOT N_PZ_653)
      OR (NOT rx_out(6) AND NOT rx_out(7) AND rx_out(5) AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0033)
      OR (NOT rx_out(6) AND NOT rx_out(7) AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0033 AND NOT N_PZ_615)
      OR (NOT rx_out(7) AND rx_out(5) AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0033 AND NOT N_PZ_911)
      OR (NOT rx_out(6) AND rx_out(5) AND
      NOT Mmult_bin_deg_mult0000__or0017 AND NOT Mmult_bin_deg_mult0000__or0023 AND NOT N_PZ_911)
      OR (NOT rx_out(6) AND NOT rx_out(5) AND
      NOT Mmult_bin_deg_mult0000__or0017 AND NOT Mmult_bin_deg_mult0000_Mxor__index0014 AND
      Mmult_bin_deg_mult0000_Mxor__index0033)
      OR (NOT rx_out(6) AND NOT rx_out(5) AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0014 AND Mmult_bin_deg_mult0000_Mxor__index0033 AND NOT N_PZ_911)
      OR (NOT rx_out(5) AND NOT Mmult_bin_deg_mult0000__or0017 AND
      NOT Mmult_bin_deg_mult0000__or0023 AND Mmult_bin_deg_mult0000_Mxor__index0033 AND NOT N_PZ_911));

Mmult_bin_deg_mult0000_Mxor__index0033 <= ((rx_out(6) AND rx_out(7) AND rx_out(5) AND N_PZ_615)
      OR (rx_out(6) AND rx_out(7) AND NOT rx_out(5) AND
      NOT Mmult_bin_deg_mult0000__or0017)
      OR (rx_out(6) AND NOT rx_out(7) AND NOT rx_out(5) AND N_PZ_615)
      OR (NOT rx_out(6) AND rx_out(7) AND NOT rx_out(5) AND NOT N_PZ_653)
      OR (NOT rx_out(6) AND NOT rx_out(7) AND rx_out(5) AND
      NOT Mmult_bin_deg_mult0000__or0017)
      OR (NOT rx_out(6) AND NOT rx_out(7) AND rx_out(5) AND NOT N_PZ_911)
      OR (rx_out(7) AND NOT rx_out(5) AND NOT N_PZ_911 AND NOT N_PZ_653)
      OR (NOT rx_out(7) AND rx_out(5) AND
      NOT Mmult_bin_deg_mult0000__or0017 AND NOT Mmult_bin_deg_mult0000__or0023 AND NOT N_PZ_615));

Mmult_bin_deg_mult0000__or0014 <= ((rx_out(0) AND rx_out(1) AND N_PZ_689)
      OR (NOT rx_out(6) AND NOT rx_out(3) AND rx_out(1) AND NOT N_PZ_619)
      OR (rx_out(3) AND NOT rx_out(4) AND rx_out(1) AND N_PZ_689)
      OR (NOT rx_out(3) AND rx_out(0) AND rx_out(1) AND NOT N_PZ_619)
      OR (rx_out(4) AND rx_out(1) AND N_PZ_689 AND N_PZ_621)
      OR (NOT rx_out(4) AND rx_out(0) AND rx_out(1) AND N_PZ_621)
      OR (rx_out(0) AND rx_out(1) AND N_PZ_619 AND N_PZ_621)
      OR (rx_out(6) AND rx_out(3) AND rx_out(4) AND rx_out(1) AND
      NOT N_PZ_621)
      OR (NOT rx_out(3) AND NOT rx_out(4) AND NOT rx_out(5) AND rx_out(1) AND
      NOT N_PZ_619)
      OR (NOT rx_out(3) AND NOT rx_out(4) AND rx_out(0) AND NOT N_PZ_689 AND
      NOT N_PZ_619)
      OR (NOT rx_out(4) AND rx_out(5) AND NOT rx_out(2) AND rx_out(0) AND
      rx_out(1))
      OR (NOT rx_out(4) AND rx_out(2) AND rx_out(1) AND N_PZ_689 AND
      NOT N_PZ_621)
      OR (rx_out(6) AND rx_out(3) AND rx_out(0) AND NOT rx_out(1) AND
      NOT N_PZ_689 AND NOT N_PZ_621)
      OR (rx_out(4) AND rx_out(0) AND NOT rx_out(1) AND NOT N_PZ_689 AND
      N_PZ_619 AND NOT N_PZ_621)
      OR (rx_out(4) AND NOT rx_out(0) AND rx_out(1) AND NOT N_PZ_689 AND
      N_PZ_619 AND NOT N_PZ_621));

Mmult_bin_deg_mult0000__or0017 <= ((NOT rx_out(4) AND
      Mmult_bin_deg_mult0000_Mxor__index0022)
      OR (NOT rx_out(3) AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0016 AND Mmult_bin_deg_mult0000_Mxor__index0021)
      OR (NOT rx_out(2) AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0016 AND Mmult_bin_deg_mult0000_Mxor__index0020 AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0015)
      OR (NOT Mmult_bin_deg_mult0000_Mxor__index0016 AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0014 AND NOT Mmult_bin_deg_mult0000__or0014 AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0015));

Mmult_bin_deg_mult0000__or00213 <= ((rx_out(0) AND NOT rx_out(1) AND N_PZ_689 AND
      Mmult_bin_deg_mult0000_Mxor__index0020)
      OR (NOT rx_out(6) AND NOT rx_out(3) AND rx_out(0) AND rx_out(1) AND
      NOT N_PZ_621)
      OR (rx_out(3) AND rx_out(4) AND rx_out(0) AND rx_out(1) AND
      NOT N_PZ_689)
      OR (NOT rx_out(3) AND rx_out(0) AND rx_out(1) AND NOT N_PZ_619 AND
      N_PZ_621)
      OR (rx_out(6) AND rx_out(3) AND NOT rx_out(4) AND rx_out(0) AND
      rx_out(1) AND NOT N_PZ_621)
      OR (rx_out(3) AND NOT rx_out(4) AND rx_out(0) AND rx_out(1) AND
      N_PZ_689 AND N_PZ_621));

Mmult_bin_deg_mult0000__or0023 <= ((NOT rx_out(3) AND
      Mmult_bin_deg_mult0000_Mxor__index0030)
      OR (NOT rx_out(2) AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0022 AND Mmult_bin_deg_mult0000_Mxor__index0029)
      OR (NOT Mmult_bin_deg_mult0000_Mxor__index0021 AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0022 AND NOT N_PZ_929));

Mmult_bin_deg_mult0000__or0028 <= ((rx_out(1) AND
      Mmult_bin_deg_mult0000_Mxor__index0029)
      OR (rx_out(0) AND rx_out(1) AND
      Mmult_bin_deg_mult0000_Mxor__index0020 AND Mmult_bin_deg_mult0000__or00213)
      OR (rx_out(0) AND rx_out(1) AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0020 AND NOT Mmult_bin_deg_mult0000__or00213)
      OR (rx_out(0) AND N_PZ_689 AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0020 AND Mmult_bin_deg_mult0000_Mxor__index0029)
      OR (rx_out(0) AND
      Mmult_bin_deg_mult0000_Mxor__index0020 AND Mmult_bin_deg_mult0000_Mxor__index0029 AND
      NOT Mmult_bin_deg_mult0000__or00213));

Mmult_bin_deg_mult0000__or0031 <= ((NOT rx_out(4) AND bin_deg(4))
      OR (NOT rx_out(3) AND bin_deg(3) AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0032)
      OR (NOT Mmult_bin_deg_mult0000_Mxor__index0031 AND NOT N_PZ_761 AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0032));

N_PZ_1003 <= (NOT u2/forward_backward AND NOT u2/cnt_reg(0) AND
u2/sensor_set_cmp_ne0000 AND NOT u2/cnt_reg(1) AND NOT N_PZ_1032);

N_PZ_1022 <= ((u4/XLXN_94)
OR (rx_out(7) AND NOT N_PZ_624 AND NOT u4/XLXN_83));

N_PZ_1032 <= (NOT data_ready AND NOT u2/run);

N_PZ_604 <= rx_out(5)
      XOR ((Mmult_bin_deg_mult0000__or0031 AND
      Mmult_bin_deg_mult0000_Mxor__index0033)
      OR (NOT Mmult_bin_deg_mult0000__or0031 AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0033));

N_PZ_606 <= rx_out(2)
      XOR ((Mmult_bin_deg_mult0000_Mxor__index0030 AND
      NOT Mmult_bin_deg_mult0000__or0028)
      OR (NOT Mmult_bin_deg_mult0000_Mxor__index0030 AND
      Mmult_bin_deg_mult0000__or0028));

N_PZ_615 <= ((N_PZ_911)
OR (Mmult_bin_deg_mult0000__or0017 AND
Mmult_bin_deg_mult0000__or0023));

N_PZ_619 <= ((NOT rx_out(6) AND NOT rx_out(5))
OR (NOT rx_out(6) AND rx_out(2)));

N_PZ_621 <= (NOT rx_out(5) AND rx_out(2));

N_PZ_624 <= ((NOT rx_out(6) AND NOT rx_out(5) AND
      Mmult_bin_deg_mult0000__or0031 AND NOT N_PZ_653)
      OR (NOT rx_out(6) AND NOT rx_out(5) AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0033 AND NOT N_PZ_653));

N_PZ_632 <= rx_out(4)
      XOR ((Mmult_bin_deg_mult0000__or0017 AND
      Mmult_bin_deg_mult0000__or0023)
      OR (NOT Mmult_bin_deg_mult0000__or0017 AND
      NOT Mmult_bin_deg_mult0000__or0023));

N_PZ_641 <= ((u4/XLXN_27 AND u4/XLXN_41)
      OR (NOT u4/XLXN_27 AND NOT u4/XLXN_41 AND NOT u4/XLXN_28)
      OR (bin_deg(3) AND N_PZ_606 AND NOT u4/XLXN_27 AND u4/XLXN_29)
      OR (NOT u4/XLXN_27 AND u4/XLXN_28 AND u4/XLXN_29 AND
      NOT u4/XLXN_35));

N_PZ_642 <= ((u2/cnt_reg(1) AND NOT rx_out(1))
OR (u2/cnt_reg(0) AND u2/cnt_reg(1) AND NOT rx_out(0))
OR (u2/cnt_reg(0) AND NOT rx_out(0) AND NOT rx_out(1)));

N_PZ_643 <= ((NOT rx_out(4) AND N_PZ_680)
OR (u2/cnt_reg(4) AND u2/Msub__sub0000__or0003));

N_PZ_653 <= (NOT Mmult_bin_deg_mult0000__or0017 AND
NOT Mmult_bin_deg_mult0000_Mxor__index0014 AND NOT Mmult_bin_deg_mult0000__or0023 AND NOT N_PZ_911);

N_PZ_666 <= ((u4/XLXN_83 AND NOT u4/XLXI_46/S1_or00007 AND NOT u4/XLXN_81)
OR (NOT u4/XLXN_83 AND N_PZ_604 AND u4/XLXI_46/S1_or00007)
OR (NOT u4/XLXN_83 AND u4/XLXI_46/S1_or00007 AND u4/XLXN_81));

N_PZ_680 <= rx_out(4)
XOR ((u2/cnt_reg(4) AND NOT u2/Msub__sub0000__or0003)
OR (NOT u2/cnt_reg(4) AND u2/Msub__sub0000__or0003));

N_PZ_689 <= ((rx_out(3) AND N_PZ_619)
      OR (NOT rx_out(4) AND N_PZ_619 AND N_PZ_621)
      OR (rx_out(6) AND rx_out(3) AND rx_out(5) AND NOT rx_out(2))
      OR (rx_out(6) AND NOT rx_out(3) AND rx_out(4) AND rx_out(2))
      OR (rx_out(6) AND NOT rx_out(3) AND NOT rx_out(4) AND rx_out(5))
      OR (rx_out(6) AND NOT rx_out(3) AND NOT rx_out(5) AND NOT rx_out(2))
      OR (NOT rx_out(6) AND NOT rx_out(3) AND rx_out(4) AND NOT N_PZ_619));

N_PZ_695 <= ((u2/cnt_reg(2) AND NOT rx_out(2))
OR (N_PZ_642 AND N_PZ_904));

N_PZ_750 <= ((u1/regrx(17) AND u1/regrx(18) AND u1/regrx(19) AND
      u1/regrx(21) AND u1/regrx(29) AND u1/regrx(31) AND u1/regrx(32) AND
      NOT u1/regrx(33) AND u1/regrx(34) AND NOT u1/regrx(35) AND u1/regrx(36) AND
      NOT u1/regrx(37) AND u1/regrx(38) AND u1/regrx(39) AND u1/regrx(1) AND
      u1/regrx(2) AND NOT u1/regrx(3) AND u1/regrx(4) AND NOT u1/regrx(5) AND
      u1/regrx(6) AND NOT u1/regrx(7) AND u1/regrx(8) AND u1/regrx(9) AND
      NOT u1/rx_out_or000047 AND NOT u1/rx_out_or000044 AND NOT N_PZ_970)
      OR (u1/regrx(17) AND u1/regrx(18) AND u1/regrx(19) AND
      u1/regrx(29) AND u1/regrx(31) AND u1/regrx(32) AND NOT u1/regrx(33) AND
      u1/regrx(34) AND NOT u1/regrx(35) AND u1/regrx(36) AND NOT u1/regrx(37) AND
      u1/regrx(38) AND u1/regrx(39) AND u1/regrx(11) AND u1/regrx(1) AND
      u1/regrx(2) AND NOT u1/regrx(3) AND u1/regrx(4) AND NOT u1/regrx(5) AND
      u1/regrx(6) AND NOT u1/regrx(7) AND u1/regrx(8) AND u1/regrx(9) AND
      NOT u1/rx_out_or000047 AND NOT u1/rx_out_or000044 AND NOT N_PZ_970)
      OR (u1/regrx(17) AND u1/regrx(19) AND u1/regrx(21) AND
      u1/regrx(28) AND u1/regrx(29) AND u1/regrx(31) AND u1/regrx(32) AND
      NOT u1/regrx(33) AND u1/regrx(34) AND NOT u1/regrx(35) AND u1/regrx(36) AND
      NOT u1/regrx(37) AND u1/regrx(38) AND u1/regrx(39) AND u1/regrx(1) AND
      u1/regrx(2) AND NOT u1/regrx(3) AND u1/regrx(4) AND NOT u1/regrx(5) AND
      u1/regrx(6) AND NOT u1/regrx(7) AND u1/regrx(8) AND u1/regrx(9) AND
      NOT u1/rx_out_or000047 AND NOT u1/rx_out_or000044 AND NOT N_PZ_970)
      OR (u1/regrx(17) AND u1/regrx(19) AND u1/regrx(28) AND
      u1/regrx(29) AND u1/regrx(31) AND u1/regrx(32) AND NOT u1/regrx(33) AND
      u1/regrx(34) AND NOT u1/regrx(35) AND u1/regrx(36) AND NOT u1/regrx(37) AND
      u1/regrx(38) AND u1/regrx(39) AND u1/regrx(11) AND u1/regrx(1) AND
      u1/regrx(2) AND NOT u1/regrx(3) AND u1/regrx(4) AND NOT u1/regrx(5) AND
      u1/regrx(6) AND NOT u1/regrx(7) AND u1/regrx(8) AND u1/regrx(9) AND
      NOT u1/rx_out_or000047 AND NOT u1/rx_out_or000044 AND NOT N_PZ_970)
      OR (u1/regrx(18) AND u1/regrx(19) AND u1/regrx(21) AND
      u1/regrx(27) AND u1/regrx(29) AND u1/regrx(31) AND u1/regrx(32) AND
      NOT u1/regrx(33) AND u1/regrx(34) AND NOT u1/regrx(35) AND u1/regrx(36) AND
      NOT u1/regrx(37) AND u1/regrx(38) AND u1/regrx(39) AND u1/regrx(1) AND
      u1/regrx(2) AND NOT u1/regrx(3) AND u1/regrx(4) AND NOT u1/regrx(5) AND
      u1/regrx(6) AND NOT u1/regrx(7) AND u1/regrx(8) AND u1/regrx(9) AND
      NOT u1/rx_out_or000047 AND NOT u1/rx_out_or000044 AND NOT N_PZ_970)
      OR (u1/regrx(18) AND u1/regrx(19) AND u1/regrx(27) AND
      u1/regrx(29) AND u1/regrx(31) AND u1/regrx(32) AND NOT u1/regrx(33) AND
      u1/regrx(34) AND NOT u1/regrx(35) AND u1/regrx(36) AND NOT u1/regrx(37) AND
      u1/regrx(38) AND u1/regrx(39) AND u1/regrx(11) AND u1/regrx(1) AND
      u1/regrx(2) AND NOT u1/regrx(3) AND u1/regrx(4) AND NOT u1/regrx(5) AND
      u1/regrx(6) AND NOT u1/regrx(7) AND u1/regrx(8) AND u1/regrx(9) AND
      NOT u1/rx_out_or000047 AND NOT u1/rx_out_or000044 AND NOT N_PZ_970)
      OR (u1/regrx(19) AND u1/regrx(21) AND u1/regrx(27) AND
      u1/regrx(28) AND u1/regrx(29) AND u1/regrx(31) AND u1/regrx(32) AND
      NOT u1/regrx(33) AND u1/regrx(34) AND NOT u1/regrx(35) AND u1/regrx(36) AND
      NOT u1/regrx(37) AND u1/regrx(38) AND u1/regrx(39) AND u1/regrx(1) AND
      u1/regrx(2) AND NOT u1/regrx(3) AND u1/regrx(4) AND NOT u1/regrx(5) AND
      u1/regrx(6) AND NOT u1/regrx(7) AND u1/regrx(8) AND u1/regrx(9) AND
      NOT u1/rx_out_or000047 AND NOT u1/rx_out_or000044 AND NOT N_PZ_970)
      OR (u1/regrx(19) AND u1/regrx(27) AND u1/regrx(28) AND
      u1/regrx(29) AND u1/regrx(31) AND u1/regrx(32) AND NOT u1/regrx(33) AND
      u1/regrx(34) AND NOT u1/regrx(35) AND u1/regrx(36) AND NOT u1/regrx(37) AND
      u1/regrx(38) AND u1/regrx(39) AND u1/regrx(11) AND u1/regrx(1) AND
      u1/regrx(2) AND NOT u1/regrx(3) AND u1/regrx(4) AND NOT u1/regrx(5) AND
      u1/regrx(6) AND NOT u1/regrx(7) AND u1/regrx(8) AND u1/regrx(9) AND
      NOT u1/rx_out_or000047 AND NOT u1/rx_out_or000044 AND NOT N_PZ_970));

N_PZ_761 <= ((rx_out(2) AND NOT N_PZ_606)
OR (Mmult_bin_deg_mult0000_Mxor__index0030 AND
Mmult_bin_deg_mult0000__or0028));

N_PZ_762 <= ((NOT rx_out(7) AND u2/cnt_reg(7) AND
      u2/Mcompar_forward_backward_cmp_lt0000_ALB20)
      OR (u2/Mcompar_forward_backward_cmp_lt0000_ALB20 AND
      u2/Msub__sub0000__or0006 AND NOT u2/SF17)
      OR (u2/Mcompar_forward_backward_cmp_lt0000_ALB20 AND
      NOT u2/Msub__sub0000__or0006 AND u2/SF17)
      OR (u2/Mcompar_forward_backward_cmp_lt0000_ALB20 AND
      u2/_sub0000(5) AND N_PZ_680 AND NOT u2/_sub0000(6))
      OR (u2/Mcompar_forward_backward_cmp_lt0000_ALB20 AND
      u2/_sub0000(5) AND u2/_sub0000(3) AND NOT u2/_sub0000(6))
      OR (u2/Mcompar_forward_backward_cmp_lt0000_ALB20 AND
      u2/_sub0000(5) AND N_PZ_642 AND N_PZ_904 AND NOT u2/_sub0000(6))
      OR (u2/Mcompar_forward_backward_cmp_lt0000_ALB20 AND
      u2/_sub0000(5) AND NOT N_PZ_642 AND NOT N_PZ_904 AND NOT u2/_sub0000(6)));

N_PZ_789 <= ((rx_out(6) AND NOT u2/cnt_reg(6))
OR (rx_out(5) AND NOT u2/cnt_reg(5)));

N_PZ_904 <= ((u2/cnt_reg(2) AND rx_out(2))
OR (NOT u2/cnt_reg(2) AND NOT rx_out(2)));

N_PZ_907 <= ((rx_out(4) AND
      Mmult_bin_deg_mult0000_Mxor__index0016)
      OR (NOT rx_out(4) AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0016));

N_PZ_911 <= (NOT rx_out(4) AND
Mmult_bin_deg_mult0000_Mxor__index0031);

N_PZ_929 <= ((Mmult_bin_deg_mult0000__or00213)
OR (rx_out(1) AND
Mmult_bin_deg_mult0000_Mxor__index0020));

N_PZ_936 <= (u3/khertz_count(0) AND u3/khertz_count(1) AND
u3/khertz_count(2) AND u3/khertz_count(4));

N_PZ_967 <= ((NOT sensor_en AND u2/sensor_set_cmp_ne0000 AND NOT N_PZ_1032)
OR (u2/sensor_set_cmp_ne0000 AND NOT N_PZ_1032 AND
NOT u2/sensor_set));

N_PZ_970 <= (NOT u1/regrx(26) AND NOT u1/regrx(16));

N_PZ_971 <= ((rx_out(4) AND NOT u2/cnt_reg(4))
OR (rx_out(3) AND rx_out(4) AND NOT u2/cnt_reg(3))
OR (rx_out(3) AND NOT u2/cnt_reg(4) AND NOT u2/cnt_reg(3)));

N_PZ_977 <= (u2/forward_backward AND u2/cnt_reg(0) AND
u2/sensor_set_cmp_ne0000 AND u2/cnt_reg(1) AND NOT N_PZ_1032);

bin_deg(1) <= ((rx_out(1) AND NOT Mmult_bin_deg_mult0000__or0028)
      OR (Mmult_bin_deg_mult0000_Mxor__index0029 AND
      NOT Mmult_bin_deg_mult0000__or0028)
      OR (rx_out(0) AND N_PZ_689 AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0020 AND NOT Mmult_bin_deg_mult0000__or0028)
      OR (rx_out(0) AND
      Mmult_bin_deg_mult0000_Mxor__index0020 AND Mmult_bin_deg_mult0000_Mxor__index0029 AND
      Mmult_bin_deg_mult0000__or00213)
      OR (rx_out(0) AND
      Mmult_bin_deg_mult0000_Mxor__index0020 AND NOT Mmult_bin_deg_mult0000_Mxor__index0029 AND
      NOT Mmult_bin_deg_mult0000__or00213)
      OR (rx_out(0) AND rx_out(1) AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0020 AND Mmult_bin_deg_mult0000_Mxor__index0029 AND
      NOT Mmult_bin_deg_mult0000__or00213));

bin_deg(3) <= rx_out(3)
XOR ((Mmult_bin_deg_mult0000_Mxor__index0031 AND NOT N_PZ_761)
OR (NOT Mmult_bin_deg_mult0000_Mxor__index0031 AND N_PZ_761));

bin_deg(4) <= ((rx_out(3) AND rx_out(4) AND N_PZ_761 AND
      Mmult_bin_deg_mult0000_Mxor__index0032)
      OR (rx_out(3) AND NOT rx_out(4) AND N_PZ_761 AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0032)
      OR (NOT rx_out(3) AND rx_out(4) AND bin_deg(3) AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0032)
      OR (NOT rx_out(3) AND NOT rx_out(4) AND bin_deg(3) AND
      Mmult_bin_deg_mult0000_Mxor__index0032)
      OR (rx_out(4) AND NOT bin_deg(3) AND
      Mmult_bin_deg_mult0000_Mxor__index0031 AND Mmult_bin_deg_mult0000_Mxor__index0032)
      OR (rx_out(4) AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0031 AND NOT N_PZ_761 AND NOT Mmult_bin_deg_mult0000_Mxor__index0032)
      OR (NOT rx_out(4) AND NOT bin_deg(3) AND
      Mmult_bin_deg_mult0000_Mxor__index0031 AND NOT Mmult_bin_deg_mult0000_Mxor__index0032)
      OR (NOT rx_out(4) AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0031 AND NOT N_PZ_761 AND Mmult_bin_deg_mult0000_Mxor__index0032));

FTCPE_clk32k: FTCPE port map (clk32k,clk32k_T,clk,'0','0','1');
     clk32k_T <= ((NOT clk32k AND NOT cnt_32k(1) AND NOT cnt_32k(5) AND NOT cnt_32k(6) AND
      NOT cnt_32k(7) AND NOT cnt_32k(8) AND NOT cnt_32k(9) AND NOT cnt_32k(10))
      OR (NOT clk32k AND NOT cnt_32k(2) AND NOT cnt_32k(5) AND NOT cnt_32k(6) AND
      NOT cnt_32k(7) AND NOT cnt_32k(8) AND NOT cnt_32k(9) AND NOT cnt_32k(10))
      OR (NOT clk32k AND NOT cnt_32k(3) AND NOT cnt_32k(5) AND NOT cnt_32k(6) AND
      NOT cnt_32k(7) AND NOT cnt_32k(8) AND NOT cnt_32k(9) AND NOT cnt_32k(10))
      OR (NOT clk32k AND NOT cnt_32k(4) AND NOT cnt_32k(5) AND NOT cnt_32k(6) AND
      NOT cnt_32k(7) AND NOT cnt_32k(8) AND NOT cnt_32k(9) AND NOT cnt_32k(10))
      OR (clk32k AND NOT cnt_32k(0) AND cnt_32k(1) AND NOT cnt_32k(2) AND
      cnt_32k(3) AND cnt_32k(4) AND cnt_32k(5) AND NOT cnt_32k(6) AND
      NOT cnt_32k(7) AND NOT cnt_32k(8) AND NOT cnt_32k(9) AND NOT cnt_32k(10)));

FTCPE_clk_div0: FTCPE port map (clk_div(0),'0',clk,'0','0','1');

FTCPE_clk_div1: FTCPE port map (clk_div(1),clk_div(0),clk,'0','0','1');

FTCPE_clk_div2: FTCPE port map (clk_div(2),clk_div_T(2),clk,'0','0','1');
clk_div_T(2) <= (clk_div(0) AND clk_div(1));

FTCPE_clk_div3: FTCPE port map (clk_div(3),clk_div_T(3),clk,'0','0','1');
clk_div_T(3) <= (clk_div(0) AND clk_div(1) AND clk_div(2));

FTCPE_clk_div4: FTCPE port map (clk_div(4),clk_div_T(4),clk,'0','0','1');
clk_div_T(4) <= (clk_div(0) AND clk_div(1) AND clk_div(2) AND
clk_div(3));

FTCPE_clk_div5: FTCPE port map (clk_div(5),clk_div_T(5),clk,'0','0','1');
clk_div_T(5) <= (clk_div(0) AND clk_div(1) AND clk_div(2) AND
clk_div(3) AND clk_div(4));

FTCPE_clk_div6: FTCPE port map (clk_div(6),clk_div_T(6),clk,'0','0','1');
clk_div_T(6) <= (clk_div(0) AND clk_div(1) AND clk_div(2) AND
clk_div(3) AND clk_div(4) AND clk_div(5));

FTCPE_clk_div7: FTCPE port map (clk_div(7),clk_div_T(7),clk,'0','0','1');
clk_div_T(7) <= (clk_div(0) AND clk_div(1) AND clk_div(2) AND
clk_div(3) AND clk_div(4) AND clk_div(5) AND clk_div(6));

FTCPE_clk_div8: FTCPE port map (clk_div(8),clk_div_T(8),clk,'0','0','1');
     clk_div_T(8) <= (clk_div(0) AND clk_div(1) AND clk_div(2) AND
      clk_div(3) AND clk_div(4) AND clk_div(5) AND clk_div(6) AND
      clk_div(7));

FTCPE_clk_div9: FTCPE port map (clk_div(9),clk_div_T(9),clk,'0','0','1');
     clk_div_T(9) <= (clk_div(0) AND clk_div(1) AND clk_div(2) AND
      clk_div(3) AND clk_div(4) AND clk_div(5) AND clk_div(6) AND
      clk_div(7) AND clk_div(8));

FTCPE_clk_div10: FTCPE port map (clk_div(10),clk_div_T(10),clk,'0','0','1');
     clk_div_T(10) <= (clk_div(0) AND clk_div(1) AND clk_div(2) AND
      clk_div(3) AND clk_div(4) AND clk_div(5) AND clk_div(6) AND
      clk_div(7) AND clk_div(8) AND clk_div(9));

FTCPE_clk_div11: FTCPE port map (clk_div(11),clk_div_T(11),clk,'0','0','1');
     clk_div_T(11) <= (clk_div(0) AND clk_div(10) AND clk_div(1) AND
      clk_div(2) AND clk_div(3) AND clk_div(4) AND clk_div(5) AND
      clk_div(6) AND clk_div(7) AND clk_div(8) AND clk_div(9));

FTCPE_clk_div12: FTCPE port map (clk_div(12),clk_div_T(12),clk,'0','0','1');
     clk_div_T(12) <= (clk_div(0) AND clk_div(10) AND clk_div(1) AND
      clk_div(2) AND clk_div(3) AND clk_div(4) AND clk_div(5) AND
      clk_div(6) AND clk_div(7) AND clk_div(8) AND clk_div(9) AND
      clk_div(11));

FTCPE_clk_div13: FTCPE port map (clk_div(13),clk_div_T(13),clk,'0','0','1');
     clk_div_T(13) <= (clk_div(0) AND clk_div(10) AND clk_div(1) AND
      clk_div(2) AND clk_div(3) AND clk_div(4) AND clk_div(5) AND
      clk_div(6) AND clk_div(7) AND clk_div(8) AND clk_div(9) AND
      clk_div(11) AND clk_div(12));

FTCPE_cnt_32k0: FTCPE port map (cnt_32k(0),cnt_32k_T(0),clk,'0','0','1');
     cnt_32k_T(0) <= NOT ((NOT cnt_32k(0) AND cnt_32k(1) AND NOT cnt_32k(2) AND
      cnt_32k(3) AND cnt_32k(4) AND cnt_32k(5) AND NOT cnt_32k(6) AND
      NOT cnt_32k(7) AND NOT cnt_32k(8) AND NOT cnt_32k(9) AND NOT cnt_32k(10)));

FTCPE_cnt_32k1: FTCPE port map (cnt_32k(1),cnt_32k_T(1),clk,'0','0','1');
     cnt_32k_T(1) <= ((cnt_32k(0))
      OR (cnt_32k(1) AND NOT cnt_32k(2) AND cnt_32k(3) AND
      cnt_32k(4) AND cnt_32k(5) AND NOT cnt_32k(6) AND NOT cnt_32k(7) AND
      NOT cnt_32k(8) AND NOT cnt_32k(9) AND NOT cnt_32k(10)));

FTCPE_cnt_32k2: FTCPE port map (cnt_32k(2),cnt_32k_T(2),clk,'0','0','1');
cnt_32k_T(2) <= (cnt_32k(0) AND cnt_32k(1));

FTCPE_cnt_32k3: FTCPE port map (cnt_32k(3),cnt_32k_T(3),clk,'0','0','1');
     cnt_32k_T(3) <= ((cnt_32k(0) AND cnt_32k(1) AND cnt_32k(2))
      OR (NOT cnt_32k(0) AND cnt_32k(1) AND NOT cnt_32k(2) AND
      cnt_32k(3) AND cnt_32k(4) AND cnt_32k(5) AND NOT cnt_32k(6) AND
      NOT cnt_32k(7) AND NOT cnt_32k(8) AND NOT cnt_32k(9) AND NOT cnt_32k(10)));

FTCPE_cnt_32k4: FTCPE port map (cnt_32k(4),cnt_32k_T(4),clk,'0','0','1');
     cnt_32k_T(4) <= ((cnt_32k(0) AND cnt_32k(1) AND cnt_32k(2) AND
      cnt_32k(3))
      OR (NOT cnt_32k(0) AND cnt_32k(1) AND NOT cnt_32k(2) AND
      cnt_32k(3) AND cnt_32k(4) AND cnt_32k(5) AND NOT cnt_32k(6) AND
      NOT cnt_32k(7) AND NOT cnt_32k(8) AND NOT cnt_32k(9) AND NOT cnt_32k(10)));

FTCPE_cnt_32k5: FTCPE port map (cnt_32k(5),cnt_32k_T(5),clk,'0','0','1');
     cnt_32k_T(5) <= ((cnt_32k(0) AND cnt_32k(1) AND cnt_32k(2) AND
      cnt_32k(3) AND cnt_32k(4))
      OR (NOT cnt_32k(0) AND cnt_32k(1) AND NOT cnt_32k(2) AND
      cnt_32k(3) AND cnt_32k(4) AND cnt_32k(5) AND NOT cnt_32k(6) AND
      NOT cnt_32k(7) AND NOT cnt_32k(8) AND NOT cnt_32k(9) AND NOT cnt_32k(10)));

FTCPE_cnt_32k6: FTCPE port map (cnt_32k(6),cnt_32k_T(6),clk,'0','0','1');
cnt_32k_T(6) <= (cnt_32k(0) AND cnt_32k(1) AND cnt_32k(2) AND
cnt_32k(3) AND cnt_32k(4) AND cnt_32k(5));

FTCPE_cnt_32k7: FTCPE port map (cnt_32k(7),cnt_32k_T(7),clk,'0','0','1');
cnt_32k_T(7) <= (cnt_32k(0) AND cnt_32k(1) AND cnt_32k(2) AND
cnt_32k(3) AND cnt_32k(4) AND cnt_32k(5) AND cnt_32k(6));

FTCPE_cnt_32k8: FTCPE port map (cnt_32k(8),cnt_32k_T(8),clk,'0','0','1');
     cnt_32k_T(8) <= (cnt_32k(0) AND cnt_32k(1) AND cnt_32k(2) AND
      cnt_32k(3) AND cnt_32k(4) AND cnt_32k(5) AND cnt_32k(6) AND
      cnt_32k(7));

FTCPE_cnt_32k9: FTCPE port map (cnt_32k(9),cnt_32k_T(9),clk,'0','0','1');
     cnt_32k_T(9) <= (cnt_32k(0) AND cnt_32k(1) AND cnt_32k(2) AND
      cnt_32k(3) AND cnt_32k(4) AND cnt_32k(5) AND cnt_32k(6) AND
      cnt_32k(7) AND cnt_32k(8));

FTCPE_cnt_32k10: FTCPE port map (cnt_32k(10),cnt_32k_T(10),clk,'0','0','1');
     cnt_32k_T(10) <= (cnt_32k(0) AND cnt_32k(1) AND cnt_32k(2) AND
      cnt_32k(3) AND cnt_32k(4) AND cnt_32k(5) AND cnt_32k(6) AND
      cnt_32k(7) AND cnt_32k(8) AND cnt_32k(9));

FTCPE_data_ready: FTCPE port map (data_ready,data_ready_T,clk32k,'0','0','1');
     data_ready_T <= ((data_ready AND u1/edge)
      OR (NOT u1/edge AND u1/clkdiv(0) AND u1/clkdiv(1) AND
      u1/clkdiv(2)));

FDCPE_digit40: FDCPE port map (digit4(0),digit4_D(0),clk,'0','0','1');
digit4_D(0) <= NOT ((NOT u3/cd(0) AND NOT u3/cd(1)));

FDCPE_digit41: FDCPE port map (digit4(1),digit4_D(1),clk,'0','0','1');
digit4_D(1) <= NOT ((u3/cd(0) AND NOT u3/cd(1)));

FDCPE_digit42: FDCPE port map (digit4(2),digit4_D(2),clk,'0','0','1');
digit4_D(2) <= NOT ((NOT u3/cd(0) AND u3/cd(1)));

FDCPE_digit43: FDCPE port map (digit4(3),digit4_D(3),clk,'0','0','1');
digit4_D(3) <= NOT ((u3/cd(0) AND u3/cd(1)));

output_mot(0) <= ((u2/run AND u2/now_ST_FFd1)
OR (u2/now_ST_FFd3 AND u2/run AND NOT u2/now_ST_FFd2));

output_mot(1) <= ((u2/run AND u2/now_ST_FFd1)
OR (NOT u2/now_ST_FFd3 AND u2/run AND u2/now_ST_FFd2));

output_mot(2) <= ((u2/now_ST_FFd3 AND u2/run AND u2/now_ST_FFd2)
OR (u2/run AND u2/now_ST_FFd2 AND u2/now_ST_FFd4));

output_mot(3) <= ((u2/run AND NOT u2/now_ST_FFd2 AND u2/now_ST_FFd4)
OR (u2/now_ST_FFd3 AND u2/run AND u2/now_ST_FFd2 AND
NOT u2/now_ST_FFd4));

FDCPE_rx_out0: FDCPE port map (rx_out(0),u1/regrx(11),data_ready,'0','0',N_PZ_750);

FDCPE_rx_out1: FDCPE port map (rx_out(1),u1/regrx(12),data_ready,'0','0',N_PZ_750);

FDCPE_rx_out2: FDCPE port map (rx_out(2),u1/regrx(13),data_ready,'0','0',N_PZ_750);

FDCPE_rx_out3: FDCPE port map (rx_out(3),u1/regrx(14),data_ready,'0','0',N_PZ_750);

FDCPE_rx_out4: FDCPE port map (rx_out(4),u1/regrx(15),data_ready,'0','0',N_PZ_750);

FDCPE_rx_out5: FDCPE port map (rx_out(5),u1/regrx(16),data_ready,'0','0',N_PZ_750);

FDCPE_rx_out6: FDCPE port map (rx_out(6),u1/regrx(17),data_ready,'0','0',N_PZ_750);

FDCPE_rx_out7: FDCPE port map (rx_out(7),u1/regrx(18),data_ready,'0','0',N_PZ_750);

FDCPE_seg40: FDCPE port map (seg4(0),u3/dp,clk,'0','0','1');

FDCPE_seg41: FDCPE port map (seg4(1),seg4_D(1),clk,'0','0','1');
     seg4_D(1) <= ((NOT u3/curr(1) AND NOT u3/curr(2) AND NOT u3/curr(3))
      OR (u3/curr(1) AND u3/curr(2) AND NOT u3/curr(3) AND
      u3/curr(0)));

FDCPE_seg42: FDCPE port map (seg4(2),seg4_D(2),clk,'0','0','1');
     seg4_D(2) <= ((u3/curr(1) AND NOT u3/curr(2) AND NOT u3/curr(3))
      OR (u3/curr(1) AND u3/curr(2) AND NOT u3/curr(3) AND
      u3/curr(0))
      OR (NOT u3/curr(1) AND NOT u3/curr(2) AND NOT u3/curr(3) AND
      u3/curr(0)));

FDCPE_seg43: FDCPE port map (seg4(3),seg4_D(3),clk,'0','0','1');
seg4_D(3) <= NOT (((u3/curr(1) AND NOT u3/curr(3) AND NOT u3/curr(0))
OR (NOT u3/curr(1) AND NOT u3/curr(2) AND NOT u3/curr(0))));

FDCPE_seg44: FDCPE port map (seg4(4),seg4_D(4),clk,'0','0','1');
     seg4_D(4) <= NOT (NOT u3/curr(2)
      XOR ((u3/curr(1) AND NOT u3/curr(2) AND u3/curr(3))
      OR (NOT u3/curr(1) AND NOT u3/curr(3) AND u3/curr(0))
      OR (u3/curr(1) AND u3/curr(2) AND NOT u3/curr(3) AND
      NOT u3/curr(0))));

FDCPE_seg45: FDCPE port map (seg4(5),seg4_D(5),clk,'0','0','1');
     seg4_D(5) <= NOT (((NOT u3/curr(1) AND NOT u3/curr(2))
      OR (u3/curr(2) AND NOT u3/curr(3))
      OR (NOT u3/curr(3) AND u3/curr(0))));

FDCPE_seg46: FDCPE port map (seg4(6),seg4_D(6),clk,'0','0','1');
     seg4_D(6) <= ((u3/curr(1) AND u3/curr(2) AND NOT u3/curr(3) AND
      NOT u3/curr(0))
      OR (NOT u3/curr(1) AND u3/curr(2) AND NOT u3/curr(3) AND
      u3/curr(0)));

FDCPE_seg47: FDCPE port map (seg4(7),seg4_D(7),clk,'0','0','1');
     seg4_D(7) <= ((NOT u3/curr(1) AND u3/curr(2) AND NOT u3/curr(3) AND
      NOT u3/curr(0))
      OR (NOT u3/curr(1) AND NOT u3/curr(2) AND NOT u3/curr(3) AND
      u3/curr(0)));

FDCPE_u1/clkdiv0: FDCPE port map (u1/clkdiv(0),u1/clkdiv_D(0),clk32k,'0','0','1');
u1/clkdiv_D(0) <= NOT ((NOT u1/edge AND u1/clkdiv(0)));

FDCPE_u1/clkdiv1: FDCPE port map (u1/clkdiv(1),u1/clkdiv_D(1),clk32k,'0','0','1');
u1/clkdiv_D(1) <= NOT (((NOT u1/edge AND u1/clkdiv(0) AND u1/clkdiv(1))
OR (NOT u1/edge AND NOT u1/clkdiv(0) AND NOT u1/clkdiv(1))));

FTCPE_u1/clkdiv2: FTCPE port map (u1/clkdiv(2),u1/clkdiv_T(2),clk32k,'0','0','1');
u1/clkdiv_T(2) <= ((u1/edge AND u1/clkdiv(2))
OR (NOT u1/edge AND u1/clkdiv(0) AND u1/clkdiv(1)));

FDCPE_u1/edge: FDCPE port map (u1/edge,u1/edge_D,clk32k,'0','0','1');
u1/edge_D <= ((u1/rxd1 AND NOT u1/rxd2)
OR (NOT u1/rxd1 AND u1/rxd2));

FDCPE_u1/regrx0: FDCPE port map (u1/regrx(0),u1/regrx(1),data_ready,'0','0','1');

FDCPE_u1/regrx1: FDCPE port map (u1/regrx(1),u1/regrx(2),data_ready,'0','0','1');

FDCPE_u1/regrx2: FDCPE port map (u1/regrx(2),u1/regrx(3),data_ready,'0','0','1');

FDCPE_u1/regrx3: FDCPE port map (u1/regrx(3),u1/regrx(4),data_ready,'0','0','1');

FDCPE_u1/regrx4: FDCPE port map (u1/regrx(4),u1/regrx(5),data_ready,'0','0','1');

FDCPE_u1/regrx5: FDCPE port map (u1/regrx(5),u1/regrx(6),data_ready,'0','0','1');

FDCPE_u1/regrx6: FDCPE port map (u1/regrx(6),u1/regrx(7),data_ready,'0','0','1');

FDCPE_u1/regrx7: FDCPE port map (u1/regrx(7),u1/regrx(8),data_ready,'0','0','1');

FDCPE_u1/regrx8: FDCPE port map (u1/regrx(8),u1/regrx(9),data_ready,'0','0','1');

FDCPE_u1/regrx9: FDCPE port map (u1/regrx(9),u1/regrx(10),data_ready,'0','0','1');

FDCPE_u1/regrx10: FDCPE port map (u1/regrx(10),u1/regrx(11),data_ready,'0','0','1');

FDCPE_u1/regrx11: FDCPE port map (u1/regrx(11),u1/regrx(12),data_ready,'0','0','1');

FDCPE_u1/regrx12: FDCPE port map (u1/regrx(12),u1/regrx(13),data_ready,'0','0','1');

FDCPE_u1/regrx13: FDCPE port map (u1/regrx(13),u1/regrx(14),data_ready,'0','0','1');

FDCPE_u1/regrx14: FDCPE port map (u1/regrx(14),u1/regrx(15),data_ready,'0','0','1');

FDCPE_u1/regrx15: FDCPE port map (u1/regrx(15),u1/regrx(16),data_ready,'0','0','1');

FDCPE_u1/regrx16: FDCPE port map (u1/regrx(16),u1/regrx(17),data_ready,'0','0','1');

FDCPE_u1/regrx17: FDCPE port map (u1/regrx(17),u1/regrx(18),data_ready,'0','0','1');

FDCPE_u1/regrx18: FDCPE port map (u1/regrx(18),u1/regrx(19),data_ready,'0','0','1');

FDCPE_u1/regrx19: FDCPE port map (u1/regrx(19),u1/regrx(20),data_ready,'0','0','1');

FDCPE_u1/regrx20: FDCPE port map (u1/regrx(20),u1/regrx(21),data_ready,'0','0','1');

FDCPE_u1/regrx21: FDCPE port map (u1/regrx(21),u1/regrx(22),data_ready,'0','0','1');

FDCPE_u1/regrx22: FDCPE port map (u1/regrx(22),u1/regrx(23),data_ready,'0','0','1');

FDCPE_u1/regrx23: FDCPE port map (u1/regrx(23),u1/regrx(24),data_ready,'0','0','1');

FDCPE_u1/regrx24: FDCPE port map (u1/regrx(24),u1/regrx(25),data_ready,'0','0','1');

FDCPE_u1/regrx25: FDCPE port map (u1/regrx(25),u1/regrx(26),data_ready,'0','0','1');

FDCPE_u1/regrx26: FDCPE port map (u1/regrx(26),u1/regrx(27),data_ready,'0','0','1');

FDCPE_u1/regrx27: FDCPE port map (u1/regrx(27),u1/regrx(28),data_ready,'0','0','1');

FDCPE_u1/regrx28: FDCPE port map (u1/regrx(28),u1/regrx(29),data_ready,'0','0','1');

FDCPE_u1/regrx29: FDCPE port map (u1/regrx(29),u1/regrx(30),data_ready,'0','0','1');

FDCPE_u1/regrx30: FDCPE port map (u1/regrx(30),u1/regrx(31),data_ready,'0','0','1');

FDCPE_u1/regrx31: FDCPE port map (u1/regrx(31),u1/regrx(32),data_ready,'0','0','1');

FDCPE_u1/regrx32: FDCPE port map (u1/regrx(32),u1/regrx(33),data_ready,'0','0','1');

FDCPE_u1/regrx33: FDCPE port map (u1/regrx(33),u1/regrx(34),data_ready,'0','0','1');

FDCPE_u1/regrx34: FDCPE port map (u1/regrx(34),u1/regrx(35),data_ready,'0','0','1');

FDCPE_u1/regrx35: FDCPE port map (u1/regrx(35),u1/regrx(36),data_ready,'0','0','1');

FDCPE_u1/regrx36: FDCPE port map (u1/regrx(36),u1/regrx(37),data_ready,'0','0','1');

FDCPE_u1/regrx37: FDCPE port map (u1/regrx(37),u1/regrx(38),data_ready,'0','0','1');

FDCPE_u1/regrx38: FDCPE port map (u1/regrx(38),u1/regrx(39),data_ready,'0','0','1');

FDCPE_u1/regrx39: FDCPE port map (u1/regrx(39),rx_data,data_ready,'0','0','1');

u1/rx_out_or000044 <= ((u1/regrx(20))
      OR (u1/regrx(30))
      OR (u1/regrx(10))
      OR (u1/regrx(0))
      OR (u1/regrx(21) AND u1/regrx(11))
      OR (u1/regrx(22) AND u1/regrx(12))
      OR (u1/regrx(23) AND u1/regrx(13))
      OR (u1/regrx(24) AND u1/regrx(14)));

u1/rx_out_or000047 <= ((u1/regrx(17) AND u1/regrx(27))
      OR (u1/regrx(18) AND u1/regrx(28))
      OR (NOT u1/regrx(22) AND NOT u1/regrx(12))
      OR (NOT u1/regrx(23) AND NOT u1/regrx(13))
      OR (NOT u1/regrx(24) AND NOT u1/regrx(14))
      OR (u1/regrx(25) AND u1/regrx(15))
      OR (NOT u1/regrx(25) AND NOT u1/regrx(15))
      OR (u1/regrx(26) AND u1/regrx(16)));

FDCPE_u1/rxd1: FDCPE port map (u1/rxd1,rx_data,clk32k,'0','0','1');

FDCPE_u1/rxd2: FDCPE port map (u1/rxd2,u1/rxd1,clk32k,'0','0','1');

u2/Mcompar_forward_backward_cmp_lt0000_ALB20 <= ((u2/SF17)
      OR (rx_out(7) AND NOT u2/Msub__sub0000__or0006 AND NOT u2/SF17)
      OR (NOT u2/cnt_reg(7) AND NOT u2/Msub__sub0000__or0006 AND
      NOT u2/SF17)
      OR (NOT rx_out(7) AND u2/cnt_reg(7) AND
      u2/Msub__sub0000__or0006 AND u2/_sub0000(5))
      OR (NOT rx_out(7) AND u2/cnt_reg(7) AND
      u2/Msub__sub0000__or0006 AND u2/_sub0000(3))
      OR (NOT rx_out(7) AND u2/cnt_reg(7) AND
      u2/Msub__sub0000__or0006 AND NOT u2/_sub0000(6))
      OR (NOT u2/_sub0000(5) AND NOT u2/_sub0000(3) AND N_PZ_695 AND
      u2/_sub0000(6))
      OR (NOT u2/_sub0000(5) AND NOT N_PZ_695 AND N_PZ_642 AND
      u2/_sub0000(6))
      OR (NOT rx_out(7) AND u2/cnt_reg(7) AND NOT u2/cnt_reg(0) AND
      rx_out(0) AND u2/Msub__sub0000__or0006)
      OR (NOT rx_out(7) AND u2/cnt_reg(7) AND NOT u2/cnt_reg(1) AND
      rx_out(1) AND u2/Msub__sub0000__or0006)
      OR (u2/cnt_reg(2) AND NOT rx_out(2) AND NOT u2/_sub0000(5) AND
      N_PZ_642 AND u2/_sub0000(6))
      OR (u2/cnt_reg(2) AND NOT u2/_sub0000(5) AND N_PZ_680 AND
      NOT N_PZ_695 AND u2/_sub0000(6))
      OR (NOT u2/cnt_reg(2) AND rx_out(2) AND NOT u2/_sub0000(5) AND
      NOT u2/_sub0000(3) AND u2/_sub0000(6))
      OR (NOT rx_out(2) AND NOT u2/_sub0000(5) AND N_PZ_680 AND
      NOT N_PZ_695 AND u2/_sub0000(6))
      OR (rx_out(7) AND u2/Msub__sub0000__or0006 AND
      NOT u2/_sub0000(5) AND NOT N_PZ_680 AND u2/_sub0000(6) AND NOT u2/SF17)
      OR (NOT rx_out(7) AND u2/cnt_reg(7) AND
      NOT u2/Msub__sub0000__or0006 AND NOT u2/_sub0000(5) AND NOT N_PZ_680 AND u2/_sub0000(6))
      OR (NOT u2/cnt_reg(7) AND u2/Msub__sub0000__or0006 AND
      NOT u2/_sub0000(5) AND NOT N_PZ_680 AND u2/_sub0000(6) AND NOT u2/SF17)
      OR (u2/cnt_reg(0) AND u2/cnt_reg(1) AND NOT u2/_sub0000(5) AND
      N_PZ_680 AND NOT N_PZ_642 AND u2/_sub0000(6))
      OR (u2/cnt_reg(0) AND NOT rx_out(1) AND NOT u2/_sub0000(5) AND
      N_PZ_680 AND NOT N_PZ_642 AND u2/_sub0000(6))
      OR (u2/cnt_reg(1) AND NOT rx_out(0) AND NOT u2/_sub0000(5) AND
      N_PZ_680 AND NOT N_PZ_642 AND u2/_sub0000(6))
      OR (NOT rx_out(0) AND NOT rx_out(1) AND NOT u2/_sub0000(5) AND
      N_PZ_680 AND NOT N_PZ_642 AND u2/_sub0000(6)));

u2/Msub__sub0000__or0003 <= ((NOT rx_out(3) AND u2/_sub0000(3))
OR (u2/cnt_reg(3) AND N_PZ_695));

u2/Msub__sub0000__or0006 <= ((NOT rx_out(6) AND u2/cnt_reg(6))
OR (NOT rx_out(5) AND u2/_sub0000(5) AND NOT N_PZ_789)
OR (u2/cnt_reg(5) AND N_PZ_643 AND NOT N_PZ_789));

u2/SF17 <= (rx_out(7) AND NOT u2/cnt_reg(7));

u2/_mux0000 <= ((u2/cnt_catch(7))
      OR (u2/cnt_catch(2) AND u2/cnt_catch(5) AND
      u2/cnt_catch(6))
      OR (u2/cnt_catch(3) AND u2/cnt_catch(5) AND
      u2/cnt_catch(6))
      OR (u2/cnt_catch(4) AND u2/cnt_catch(5) AND
      u2/cnt_catch(6))
      OR (NOT u2/cnt_catch(2) AND NOT u2/cnt_catch(3) AND
      NOT u2/cnt_catch(4) AND NOT u2/cnt_catch(5) AND NOT u2/cnt_catch(6) AND
      NOT u2/cnt_catch(0) AND NOT u2/cnt_catch(1)));

u2/_sub0000(3) <= rx_out(3)
XOR ((u2/cnt_reg(3) AND NOT N_PZ_695)
OR (NOT u2/cnt_reg(3) AND N_PZ_695));

u2/_sub0000(5) <= rx_out(5)
XOR ((u2/cnt_reg(5) AND NOT N_PZ_643)
OR (NOT u2/cnt_reg(5) AND N_PZ_643));

u2/_sub0000(6) <= ((NOT rx_out(6) AND NOT u2/Msub__sub0000__or0006)
      OR (u2/cnt_reg(6) AND NOT u2/Msub__sub0000__or0006)
      OR (NOT rx_out(5) AND NOT u2/Msub__sub0000__or0006 AND
      u2/_sub0000(5))
      OR (u2/cnt_reg(5) AND NOT u2/Msub__sub0000__or0006 AND
      N_PZ_643)
      OR (NOT rx_out(6) AND NOT rx_out(5) AND u2/cnt_reg(6) AND
      u2/_sub0000(5))
      OR (NOT rx_out(6) AND u2/cnt_reg(6) AND u2/cnt_reg(5) AND
      N_PZ_643));

FDCPE_u2/cnt_catch0: FDCPE port map (u2/cnt_catch(0),rx_out(0),data_ready,'0','0',NOT u2/cnt_catch_cmp_le0000);

FDCPE_u2/cnt_catch1: FDCPE port map (u2/cnt_catch(1),rx_out(1),data_ready,'0','0',NOT u2/cnt_catch_cmp_le0000);

FDCPE_u2/cnt_catch2: FDCPE port map (u2/cnt_catch(2),rx_out(2),data_ready,'0','0',NOT u2/cnt_catch_cmp_le0000);

FDCPE_u2/cnt_catch3: FDCPE port map (u2/cnt_catch(3),rx_out(3),data_ready,'0','0',NOT u2/cnt_catch_cmp_le0000);

FDCPE_u2/cnt_catch4: FDCPE port map (u2/cnt_catch(4),rx_out(4),data_ready,'0','0',NOT u2/cnt_catch_cmp_le0000);

FDCPE_u2/cnt_catch5: FDCPE port map (u2/cnt_catch(5),rx_out(5),data_ready,'0','0',NOT u2/cnt_catch_cmp_le0000);

FDCPE_u2/cnt_catch6: FDCPE port map (u2/cnt_catch(6),rx_out(6),data_ready,'0','0',NOT u2/cnt_catch_cmp_le0000);

FDCPE_u2/cnt_catch7: FDCPE port map (u2/cnt_catch(7),rx_out(7),data_ready,'0','0',NOT u2/cnt_catch_cmp_le0000);

u2/cnt_catch_cmp_le0000 <= (rx_out(6) AND rx_out(7))
XOR (rx_out(6) AND rx_out(7) AND NOT rx_out(3) AND NOT rx_out(4) AND
NOT rx_out(5));

FTCPE_u2/cnt_reg0: FTCPE port map (u2/cnt_reg(0),u2/cnt_reg_T(0),clk_div(13),u2/cnt_reg_CLR(0),'0','1');
u2/cnt_reg_T(0) <= (u2/sensor_set_cmp_ne0000 AND NOT N_PZ_1032);
u2/cnt_reg_CLR(0) <= (sensor_en AND u2/sensor_set);

FTCPE_u2/cnt_reg1: FTCPE port map (u2/cnt_reg(1),u2/cnt_reg_T(1),clk_div(13),u2/cnt_reg_CLR(1),'0','1');
     u2/cnt_reg_T(1) <= ((u2/forward_backward AND u2/cnt_reg(0) AND
      u2/sensor_set_cmp_ne0000 AND NOT N_PZ_1032)
      OR (NOT u2/forward_backward AND NOT u2/cnt_reg(0) AND
      u2/sensor_set_cmp_ne0000 AND NOT N_PZ_1032));
     u2/cnt_reg_CLR(1) <= (sensor_en AND u2/sensor_set);

FTCPE_u2/cnt_reg2: FTCPE port map (u2/cnt_reg(2),u2/cnt_reg_T(2),clk_div(13),u2/cnt_reg_CLR(2),'0','1');
u2/cnt_reg_T(2) <= NOT ((NOT N_PZ_977 AND NOT N_PZ_1003));
u2/cnt_reg_CLR(2) <= (sensor_en AND u2/sensor_set);

FTCPE_u2/cnt_reg3: FTCPE port map (u2/cnt_reg(3),u2/cnt_reg_T(3),clk_div(13),u2/cnt_reg_CLR(3),'0','1');
     u2/cnt_reg_T(3) <= NOT (((u2/cnt_reg(2) AND NOT N_PZ_977)
      OR (NOT u2/cnt_reg(2) AND NOT N_PZ_1003)
      OR (u2/cnt_reg(7) AND NOT u2/cnt_reg(4) AND u2/cnt_reg(2) AND
      NOT u2/cnt_reg(3) AND u2/cnt_reg(6) AND NOT u2/cnt_reg(5))
      OR (NOT u2/cnt_reg(7) AND NOT u2/cnt_reg(4) AND NOT u2/cnt_reg(2) AND
      NOT u2/cnt_reg(3) AND NOT u2/cnt_reg(6) AND NOT u2/cnt_reg(5))));
     u2/cnt_reg_CLR(3) <= (sensor_en AND u2/sensor_set);

FTCPE_u2/cnt_reg4: FTCPE port map (u2/cnt_reg(4),u2/cnt_reg_T(4),clk_div(13),u2/cnt_reg_CLR(4),'0','1');
     u2/cnt_reg_T(4) <= (NOT u2/cnt_reg(2) AND NOT u2/cnt_reg(3) AND N_PZ_1003)
      XOR ((u2/cnt_reg(2) AND N_PZ_977 AND u2/cnt_reg(3))
      OR (NOT u2/cnt_reg(7) AND NOT u2/cnt_reg(4) AND NOT u2/cnt_reg(2) AND
      NOT u2/cnt_reg(3) AND NOT u2/cnt_reg(6) AND NOT u2/cnt_reg(5) AND N_PZ_1003));
     u2/cnt_reg_CLR(4) <= (sensor_en AND u2/sensor_set);

FTCPE_u2/cnt_reg5: FTCPE port map (u2/cnt_reg(5),u2/cnt_reg_T(5),clk_div(13),u2/cnt_reg_CLR(5),'0','1');
     u2/cnt_reg_T(5) <= ((u2/cnt_reg(4) AND u2/cnt_reg(2) AND N_PZ_977 AND
      u2/cnt_reg(3))
      OR (u2/cnt_reg(7) AND NOT u2/cnt_reg(4) AND NOT u2/cnt_reg(2) AND
      NOT u2/cnt_reg(3) AND N_PZ_1003)
      OR (NOT u2/cnt_reg(4) AND NOT u2/cnt_reg(2) AND NOT u2/cnt_reg(3) AND
      u2/cnt_reg(6) AND N_PZ_1003)
      OR (NOT u2/cnt_reg(4) AND NOT u2/cnt_reg(2) AND NOT u2/cnt_reg(3) AND
      u2/cnt_reg(5) AND N_PZ_1003));
     u2/cnt_reg_CLR(5) <= (sensor_en AND u2/sensor_set);

FTCPE_u2/cnt_reg6: FTCPE port map (u2/cnt_reg(6),u2/cnt_reg_T(6),clk_div(13),u2/cnt_reg_CLR(6),'0','1');
     u2/cnt_reg_T(6) <= ((u2/cnt_reg(4) AND u2/cnt_reg(2) AND N_PZ_977 AND
      u2/cnt_reg(3) AND u2/cnt_reg(5))
      OR (NOT u2/cnt_reg(4) AND NOT u2/cnt_reg(2) AND NOT u2/cnt_reg(3) AND
      NOT u2/cnt_reg(5) AND N_PZ_1003)
      OR (u2/cnt_reg(7) AND NOT u2/cnt_reg(4) AND u2/cnt_reg(2) AND
      N_PZ_977 AND NOT u2/cnt_reg(3) AND u2/cnt_reg(6) AND NOT u2/cnt_reg(5)));
     u2/cnt_reg_CLR(6) <= (sensor_en AND u2/sensor_set);

FTCPE_u2/cnt_reg7: FTCPE port map (u2/cnt_reg(7),u2/cnt_reg_T(7),clk_div(13),u2/cnt_reg_CLR(7),'0','1');
     u2/cnt_reg_T(7) <= ((u2/cnt_reg(4) AND u2/cnt_reg(2) AND N_PZ_977 AND
      u2/cnt_reg(3) AND u2/cnt_reg(6) AND u2/cnt_reg(5))
      OR (NOT u2/cnt_reg(4) AND NOT u2/cnt_reg(2) AND NOT u2/cnt_reg(3) AND
      NOT u2/cnt_reg(6) AND NOT u2/cnt_reg(5) AND N_PZ_1003)
      OR (u2/cnt_reg(7) AND NOT u2/cnt_reg(4) AND u2/cnt_reg(2) AND
      N_PZ_977 AND NOT u2/cnt_reg(3) AND u2/cnt_reg(6) AND NOT u2/cnt_reg(5)));
     u2/cnt_reg_CLR(7) <= (sensor_en AND u2/sensor_set);

FDCPE_u2/forward_backward: FDCPE port map (u2/forward_backward,u2/forward_backward_D,data_ready,u2/forward_backward_CLR,u2/forward_backward_PRE,'1');
     u2/forward_backward_D <= NOT (((NOT u2/forward_backward AND u2/cnt_catch_cmp_le0000)
      OR (NOT u2/cnt_catch_cmp_le0000 AND sensor_en AND
      u2/_mux0000)
      OR (NOT u2/cnt_catch_cmp_le0000 AND NOT sensor_en AND
      NOT u2/forward_backward_mux000876 AND N_PZ_762)
      OR (NOT rx_out(7) AND NOT sensor_en AND u2/cnt_reg(7) AND
      NOT u2/forward_backward_mux000876)
      OR (NOT rx_out(6) AND NOT sensor_en AND u2/cnt_reg(6) AND
      NOT u2/forward_backward_mux000876 AND NOT u2/SF17)
      OR (NOT u2/cnt_catch_cmp_le0000 AND NOT rx_out(5) AND NOT sensor_en AND
      u2/cnt_reg(5) AND NOT u2/forward_backward_mux000876 AND NOT N_PZ_789 AND
      NOT u2/SF17)
      OR (NOT u2/cnt_catch_cmp_le0000 AND NOT rx_out(3) AND NOT sensor_en AND
      u2/cnt_reg(3) AND NOT u2/forward_backward_mux000876 AND NOT N_PZ_789 AND
      NOT u2/SF17 AND NOT N_PZ_971)
      OR (NOT u2/cnt_catch_cmp_le0000 AND NOT rx_out(4) AND NOT sensor_en AND
      u2/cnt_reg(4) AND NOT u2/forward_backward_mux000876 AND NOT N_PZ_789 AND
      NOT u2/SF17 AND NOT N_PZ_971)
      OR (NOT u2/cnt_catch_cmp_le0000 AND NOT sensor_en AND
      u2/cnt_reg(2) AND NOT rx_out(2) AND NOT u2/forward_backward_mux000876 AND
      NOT N_PZ_789 AND NOT u2/SF17 AND NOT N_PZ_971)
      OR (NOT u2/cnt_catch_cmp_le0000 AND NOT sensor_en AND
      u2/cnt_reg(0) AND u2/cnt_reg(1) AND NOT u2/forward_backward_mux000876 AND
      N_PZ_904 AND NOT N_PZ_789 AND NOT u2/SF17 AND NOT N_PZ_971)
      OR (NOT u2/cnt_catch_cmp_le0000 AND NOT sensor_en AND
      u2/cnt_reg(0) AND NOT rx_out(1) AND NOT u2/forward_backward_mux000876 AND
      N_PZ_904 AND NOT N_PZ_789 AND NOT u2/SF17 AND NOT N_PZ_971)
      OR (NOT u2/cnt_catch_cmp_le0000 AND NOT sensor_en AND
      u2/cnt_reg(1) AND NOT rx_out(0) AND NOT u2/forward_backward_mux000876 AND
      N_PZ_904 AND NOT N_PZ_789 AND NOT u2/SF17 AND NOT N_PZ_971)
      OR (NOT u2/cnt_catch_cmp_le0000 AND NOT sensor_en AND
      u2/cnt_reg(1) AND NOT rx_out(1) AND NOT u2/forward_backward_mux000876 AND
      N_PZ_904 AND NOT N_PZ_789 AND NOT u2/SF17 AND NOT N_PZ_971)
      OR (NOT u2/cnt_catch_cmp_le0000 AND NOT sensor_en AND NOT rx_out(0) AND
      NOT rx_out(1) AND NOT u2/forward_backward_mux000876 AND N_PZ_904 AND
      NOT N_PZ_789 AND NOT u2/SF17 AND NOT N_PZ_971)));
     u2/forward_backward_CLR <= (sensor_en AND u2/_mux0000);
     u2/forward_backward_PRE <= (sensor_en AND NOT u2/_mux0000);

u2/forward_backward_mux000876 <= ((NOT rx_out(7) AND u2/cnt_reg(7) AND N_PZ_762)
      OR (NOT rx_out(6) AND u2/cnt_reg(6) AND N_PZ_762 AND NOT u2/SF17)
      OR (N_PZ_762 AND N_PZ_643 AND NOT N_PZ_789 AND NOT u2/SF17)
      OR (NOT rx_out(5) AND u2/cnt_reg(5) AND N_PZ_762 AND NOT N_PZ_789 AND
      NOT u2/SF17));

FDCPE_u2/now_ST_FFd1: FDCPE port map (u2/now_ST_FFd1,u2/now_ST_FFd1_D,clk_div(13),'0','0','1');
     u2/now_ST_FFd1_D <= ((NOT N_PZ_967 AND u2/now_ST_FFd1)
      OR (u2/now_ST_FFd3 AND NOT u2/forward_backward AND N_PZ_967 AND
      NOT u2/now_ST_FFd2 AND NOT u2/now_ST_FFd4)
      OR (NOT u2/now_ST_FFd3 AND u2/forward_backward AND N_PZ_967 AND
      u2/now_ST_FFd2 AND NOT u2/now_ST_FFd4 AND NOT u2/now_ST_FFd1));

FTCPE_u2/now_ST_FFd2: FTCPE port map (u2/now_ST_FFd2,u2/now_ST_FFd2_T,clk_div(13),'0','0','1');
     u2/now_ST_FFd2_T <= ((NOT u2/forward_backward AND N_PZ_967 AND NOT u2/now_ST_FFd2 AND
      u2/now_ST_FFd1)
      OR (u2/now_ST_FFd3 AND NOT u2/forward_backward AND N_PZ_967 AND
      NOT u2/now_ST_FFd4 AND NOT u2/now_ST_FFd1)
      OR (NOT u2/now_ST_FFd3 AND u2/forward_backward AND N_PZ_967 AND
      NOT u2/now_ST_FFd2 AND u2/now_ST_FFd4)
      OR (NOT u2/now_ST_FFd3 AND u2/forward_backward AND N_PZ_967 AND
      u2/now_ST_FFd2 AND NOT u2/now_ST_FFd4 AND u2/now_ST_FFd1));

FDCPE_u2/now_ST_FFd3: FDCPE port map (u2/now_ST_FFd3,u2/now_ST_FFd3_D,clk_div(13),'0','0','1');
     u2/now_ST_FFd3_D <= NOT (((NOT u2/now_ST_FFd3 AND NOT N_PZ_967)
      OR (NOT u2/now_ST_FFd3 AND NOT u2/now_ST_FFd4 AND NOT u2/now_ST_FFd1)
      OR (NOT u2/forward_backward AND N_PZ_967 AND NOT u2/now_ST_FFd4)
      OR (NOT u2/now_ST_FFd3 AND u2/forward_backward AND
      u2/now_ST_FFd2 AND NOT u2/now_ST_FFd1)
      OR (u2/now_ST_FFd3 AND u2/forward_backward AND N_PZ_967 AND
      u2/now_ST_FFd4 AND NOT u2/now_ST_FFd1)));

FDCPE_u2/now_ST_FFd4: FDCPE port map (u2/now_ST_FFd4,u2/now_ST_FFd4_D,clk_div(13),'0','0','1');
     u2/now_ST_FFd4_D <= NOT (((NOT N_PZ_967 AND NOT u2/now_ST_FFd4)
      OR (u2/now_ST_FFd3 AND NOT u2/forward_backward AND N_PZ_967 AND
      u2/now_ST_FFd4)
      OR (u2/now_ST_FFd3 AND NOT u2/forward_backward AND
      NOT u2/now_ST_FFd2 AND NOT u2/now_ST_FFd4)
      OR (NOT u2/now_ST_FFd3 AND u2/forward_backward AND N_PZ_967 AND
      u2/now_ST_FFd4)
      OR (NOT u2/now_ST_FFd3 AND u2/forward_backward AND
      u2/now_ST_FFd2 AND NOT u2/now_ST_FFd4)
      OR (NOT u2/now_ST_FFd3 AND u2/now_ST_FFd2 AND NOT u2/now_ST_FFd4 AND
      u2/now_ST_FFd1)));

FDCPE_u2/run: FDCPE port map (u2/run,u2/run_D,clk_div(13),'0','0','1');
u2/run_D <= ((N_PZ_967)
OR (sensor_en AND u2/run AND u2/sensor_set));

FTCPE_u2/sensor_set: FTCPE port map (u2/sensor_set,u2/sensor_set_T,clk_div(13),u2/sensor_set_CLR,'0','1');
     u2/sensor_set_T <= (NOT u2/sensor_set_cmp_ne0000 AND NOT N_PZ_1032 AND
      NOT u2/sensor_set);
     u2/sensor_set_CLR <= (sensor_en AND u2/sensor_set);

u2/sensor_set_cmp_ne0000 <= ((u2/cnt_reg(7) AND NOT u2/cnt_catch(7))
      OR (NOT u2/cnt_reg(7) AND u2/cnt_catch(7))
      OR (u2/cnt_reg(4) AND NOT u2/cnt_catch(4))
      OR (NOT u2/cnt_reg(4) AND u2/cnt_catch(4))
      OR (u2/cnt_reg(2) AND NOT u2/cnt_catch(2))
      OR (NOT u2/cnt_reg(2) AND u2/cnt_catch(2))
      OR (u2/cnt_reg(0) AND NOT u2/cnt_catch(0))
      OR (NOT u2/cnt_reg(0) AND u2/cnt_catch(0))
      OR (u2/cnt_reg(3) AND NOT u2/cnt_catch(3))
      OR (NOT u2/cnt_reg(3) AND u2/cnt_catch(3))
      OR (u2/cnt_reg(6) AND NOT u2/cnt_catch(6))
      OR (NOT u2/cnt_reg(6) AND u2/cnt_catch(6))
      OR (u2/cnt_reg(5) AND NOT u2/cnt_catch(5))
      OR (NOT u2/cnt_reg(5) AND u2/cnt_catch(5))
      OR (u2/cnt_reg(1) AND NOT u2/cnt_catch(1))
      OR (NOT u2/cnt_reg(1) AND u2/cnt_catch(1)));

FTCPE_u3/cd0: FTCPE port map (u3/cd(0),u3/khertz_en,clk,'0','0','1');

FTCPE_u3/cd1: FTCPE port map (u3/cd(1),u3/cd_T(1),clk,'0','0','1');
u3/cd_T(1) <= (u3/cd(0) AND u3/khertz_en);

FDCPE_u3/curr0: FDCPE port map (u3/curr(0),u3/curr_D(0),clk,'0','0','1');
     u3/curr_D(0) <= ((NOT u3/cd(0) AND NOT u3/cd(1))
      OR (NOT u3/cd(0) AND u4/XLXN_35 AND NOT u4/XLXN_34 AND NOT u4/XLXN_33)
      OR (NOT u3/cd(0) AND NOT u4/XLXN_35 AND u4/XLXN_34 AND bin_deg(1))
      OR (NOT u3/cd(0) AND NOT u4/XLXN_35 AND u4/XLXN_34 AND u4/XLXN_33)
      OR (u3/cd(0) AND u3/cd(1) AND u4/XLXN_36 AND u4/XLXN_37 AND
      u4/XLXN_38)
      OR (u3/cd(0) AND u3/cd(1) AND NOT u4/XLXN_36 AND NOT u4/XLXN_37 AND
      N_PZ_641)
      OR (u3/cd(0) AND u3/cd(1) AND NOT u4/XLXN_36 AND NOT u4/XLXN_37 AND
      NOT u4/XLXN_38)
      OR (NOT u3/cd(1) AND rx_out(0) AND rx_out(1) AND
      Mmult_bin_deg_mult0000_Mxor__index0020 AND NOT Mmult_bin_deg_mult0000__or00213)
      OR (NOT u3/cd(1) AND rx_out(0) AND rx_out(1) AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0020 AND Mmult_bin_deg_mult0000__or00213)
      OR (NOT u3/cd(1) AND rx_out(0) AND NOT rx_out(1) AND NOT N_PZ_689 AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0020)
      OR (NOT u3/cd(1) AND rx_out(0) AND NOT rx_out(1) AND
      Mmult_bin_deg_mult0000_Mxor__index0020 AND Mmult_bin_deg_mult0000__or00213)
      OR (NOT u3/cd(1) AND NOT rx_out(0) AND rx_out(1) AND
      Mmult_bin_deg_mult0000_Mxor__index0020 AND Mmult_bin_deg_mult0000__or00213)
      OR (NOT u3/cd(1) AND NOT rx_out(0) AND rx_out(1) AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0020 AND NOT N_PZ_929)
      OR (NOT u3/cd(1) AND NOT rx_out(0) AND NOT rx_out(1) AND
      Mmult_bin_deg_mult0000_Mxor__index0020 AND NOT Mmult_bin_deg_mult0000__or00213));

FDCPE_u3/curr1: FDCPE port map (u3/curr(1),u3/curr_D(1),clk,'0','0','1');
     u3/curr_D(1) <= ((NOT u3/cd(0) AND NOT u3/cd(1))
      OR (NOT u3/cd(0) AND NOT u4/XLXN_36 AND u4/XLXN_37 AND N_PZ_641)
      OR (NOT u3/cd(1) AND NOT u4/XLXN_35 AND NOT u4/XLXN_34 AND bin_deg(1))
      OR (u3/cd(0) AND u3/cd(1) AND NOT u4/XLXI_47/S0_or000011 AND
      N_PZ_666 AND NOT u4/XLXN_36)
      OR (NOT u3/cd(0) AND NOT u4/XLXN_36 AND NOT u4/XLXN_37 AND NOT N_PZ_641 AND
      NOT u4/XLXN_38)
      OR (NOT u3/cd(1) AND u4/XLXN_35 AND NOT u4/XLXN_34 AND NOT bin_deg(1) AND
      NOT u4/XLXN_33)
      OR (NOT u3/cd(1) AND NOT u4/XLXN_35 AND u4/XLXN_34 AND NOT bin_deg(1) AND
      u4/XLXN_33)
      OR (NOT u3/cd(0) AND u3/cd(1) AND u4/XLXN_36 AND u4/XLXN_37 AND
      NOT N_PZ_641 AND u4/XLXN_38)
      OR (u3/cd(0) AND u3/cd(1) AND rx_out(7) AND NOT N_PZ_624 AND
      NOT u4/XLXN_83 AND NOT u4/XLXI_47/S0_or000011 AND NOT N_PZ_666 AND u4/XLXN_94));

FDCPE_u3/curr2: FDCPE port map (u3/curr(2),u3/curr_D(2),clk,'0','0','1');
     u3/curr_D(2) <= ((u3/cd(0) AND NOT u3/cd(1) AND NOT u4/XLXN_35 AND NOT u4/XLXN_34 AND
      u4/XLXN_33)
      OR (u3/cd(0) AND NOT u3/cd(1) AND NOT u4/XLXN_35 AND bin_deg(1) AND
      u4/XLXN_33)
      OR (NOT u3/cd(0) AND u3/cd(1) AND NOT u4/XLXN_36 AND u4/XLXN_37 AND
      NOT u4/XLXN_38)
      OR (NOT u3/cd(0) AND u3/cd(1) AND NOT u4/XLXN_36 AND N_PZ_641 AND
      NOT u4/XLXN_38)
      OR (u3/cd(0) AND u3/cd(1) AND rx_out(7) AND NOT N_PZ_624 AND
      NOT u4/XLXN_83 AND N_PZ_666)
      OR (u3/cd(0) AND u3/cd(1) AND rx_out(7) AND NOT N_PZ_624 AND
      NOT u4/XLXN_83 AND NOT u4/XLXN_94)
      OR (u3/cd(0) AND NOT u3/cd(1) AND u4/XLXN_35 AND NOT u4/XLXN_34 AND
      NOT bin_deg(1) AND NOT u4/XLXN_33)
      OR (NOT u3/cd(0) AND u3/cd(1) AND u4/XLXN_36 AND u4/XLXN_37 AND
      NOT N_PZ_641 AND u4/XLXN_38));

FDCPE_u3/curr3: FDCPE port map (u3/curr(3),u3/curr_D(3),clk,'0','0','1');
     u3/curr_D(3) <= ((NOT u3/cd(0) AND NOT u3/cd(1))
      OR (NOT u3/cd(0) AND u4/XLXN_36 AND u4/XLXN_37 AND N_PZ_641 AND
      u4/XLXN_38)
      OR (NOT u3/cd(0) AND NOT u4/XLXN_36 AND NOT u4/XLXN_37 AND NOT N_PZ_641 AND
      u4/XLXN_38)
      OR (NOT u3/cd(1) AND u4/XLXN_35 AND NOT u4/XLXN_34 AND bin_deg(1) AND
      NOT u4/XLXN_33)
      OR (NOT u3/cd(1) AND NOT u4/XLXN_35 AND u4/XLXN_34 AND NOT bin_deg(1) AND
      NOT u4/XLXN_33));

FDCPE_u3/dp: FDCPE port map (u3/dp,NOT '0',clk,'0','0','1');

FTCPE_u3/khertz_count0: FTCPE port map (u3/khertz_count(0),u3/khertz_count_T(0),clk,'0','0','1');
     u3/khertz_count_T(0) <= NOT (((NOT u3/mhertz_en)
      OR (NOT u3/khertz_count(0) AND NOT u3/khertz_count(1) AND
      NOT u3/khertz_count(2) AND u3/khertz_count(3) AND NOT u3/khertz_count(4) AND
      u3/khertz_count(5) AND u3/khertz_count(6) AND u3/khertz_count(7) AND
      u3/khertz_count(8) AND u3/khertz_count(9))));

FTCPE_u3/khertz_count1: FTCPE port map (u3/khertz_count(1),u3/khertz_count_T(1),clk,'0','0','1');
u3/khertz_count_T(1) <= (u3/khertz_count(0) AND u3/mhertz_en);

FTCPE_u3/khertz_count2: FTCPE port map (u3/khertz_count(2),u3/khertz_count_T(2),clk,'0','0','1');
u3/khertz_count_T(2) <= (u3/khertz_count(0) AND u3/khertz_count(1) AND
u3/mhertz_en);

FTCPE_u3/khertz_count3: FTCPE port map (u3/khertz_count(3),u3/khertz_count_T(3),clk,'0','0','1');
     u3/khertz_count_T(3) <= ((u3/khertz_count(0) AND u3/khertz_count(1) AND
      u3/mhertz_en AND u3/khertz_count(2))
      OR (NOT u3/khertz_count(0) AND NOT u3/khertz_count(1) AND
      u3/mhertz_en AND NOT u3/khertz_count(2) AND u3/khertz_count(3) AND
      NOT u3/khertz_count(4) AND u3/khertz_count(5) AND u3/khertz_count(6) AND
      u3/khertz_count(7) AND u3/khertz_count(8) AND u3/khertz_count(9)));

FTCPE_u3/khertz_count4: FTCPE port map (u3/khertz_count(4),u3/khertz_count_T(4),clk,'0','0','1');
u3/khertz_count_T(4) <= (u3/khertz_count(0) AND u3/khertz_count(1) AND
u3/mhertz_en AND u3/khertz_count(2) AND u3/khertz_count(3));

FDCPE_u3/khertz_count5: FDCPE port map (u3/khertz_count(5),u3/khertz_count_D(5),clk,'0','0','1');
     u3/khertz_count_D(5) <= NOT (((NOT u3/mhertz_en AND NOT u3/khertz_count(5))
      OR (NOT u3/khertz_count(3) AND NOT u3/khertz_count(5))
      OR (NOT u3/khertz_count(5) AND NOT N_PZ_936)
      OR (u3/mhertz_en AND u3/khertz_count(3) AND
      u3/khertz_count(5) AND N_PZ_936)
      OR (NOT u3/khertz_count(0) AND NOT u3/khertz_count(1) AND
      u3/mhertz_en AND NOT u3/khertz_count(2) AND u3/khertz_count(3) AND
      NOT u3/khertz_count(4) AND u3/khertz_count(6) AND u3/khertz_count(7) AND
      u3/khertz_count(8) AND u3/khertz_count(9))));

FDCPE_u3/khertz_count6: FDCPE port map (u3/khertz_count(6),u3/khertz_count_D(6),clk,'0','0','1');
     u3/khertz_count_D(6) <= NOT (((NOT u3/mhertz_en AND NOT u3/khertz_count(6))
      OR (NOT u3/khertz_count(3) AND NOT u3/khertz_count(6))
      OR (NOT u3/khertz_count(5) AND NOT u3/khertz_count(6))
      OR (NOT u3/khertz_count(6) AND NOT N_PZ_936)
      OR (u3/mhertz_en AND u3/khertz_count(3) AND
      u3/khertz_count(5) AND u3/khertz_count(6) AND N_PZ_936)
      OR (NOT u3/khertz_count(0) AND NOT u3/khertz_count(1) AND
      u3/mhertz_en AND NOT u3/khertz_count(2) AND u3/khertz_count(3) AND
      NOT u3/khertz_count(4) AND u3/khertz_count(5) AND u3/khertz_count(7) AND
      u3/khertz_count(8) AND u3/khertz_count(9))));

FDCPE_u3/khertz_count7: FDCPE port map (u3/khertz_count(7),u3/khertz_count_D(7),clk,'0','0','1');
     u3/khertz_count_D(7) <= NOT (((NOT u3/mhertz_en AND NOT u3/khertz_count(7))
      OR (NOT u3/khertz_count(3) AND NOT u3/khertz_count(7))
      OR (NOT u3/khertz_count(5) AND NOT u3/khertz_count(7))
      OR (NOT u3/khertz_count(6) AND NOT u3/khertz_count(7))
      OR (NOT u3/khertz_count(7) AND NOT N_PZ_936)
      OR (u3/mhertz_en AND u3/khertz_count(3) AND
      u3/khertz_count(5) AND u3/khertz_count(6) AND u3/khertz_count(7) AND
      N_PZ_936)
      OR (NOT u3/khertz_count(0) AND NOT u3/khertz_count(1) AND
      u3/mhertz_en AND NOT u3/khertz_count(2) AND u3/khertz_count(3) AND
      NOT u3/khertz_count(4) AND u3/khertz_count(5) AND u3/khertz_count(6) AND
      u3/khertz_count(8) AND u3/khertz_count(9))));

FTCPE_u3/khertz_count8: FTCPE port map (u3/khertz_count(8),u3/khertz_count_T(8),clk,'0','0','1');
     u3/khertz_count_T(8) <= ((u3/mhertz_en AND u3/khertz_count(3) AND
      u3/khertz_count(5) AND u3/khertz_count(6) AND u3/khertz_count(7) AND
      N_PZ_936)
      OR (NOT u3/khertz_count(0) AND NOT u3/khertz_count(1) AND
      u3/mhertz_en AND NOT u3/khertz_count(2) AND u3/khertz_count(3) AND
      NOT u3/khertz_count(4) AND u3/khertz_count(5) AND u3/khertz_count(6) AND
      u3/khertz_count(7) AND u3/khertz_count(8) AND u3/khertz_count(9)));

FTCPE_u3/khertz_count9: FTCPE port map (u3/khertz_count(9),u3/khertz_count_T(9),clk,'0','0','1');
     u3/khertz_count_T(9) <= ((u3/mhertz_en AND u3/khertz_count(3) AND
      u3/khertz_count(5) AND u3/khertz_count(6) AND u3/khertz_count(7) AND
      u3/khertz_count(8) AND N_PZ_936)
      OR (NOT u3/khertz_count(0) AND NOT u3/khertz_count(1) AND
      u3/mhertz_en AND NOT u3/khertz_count(2) AND u3/khertz_count(3) AND
      NOT u3/khertz_count(4) AND u3/khertz_count(5) AND u3/khertz_count(6) AND
      u3/khertz_count(7) AND u3/khertz_count(8) AND u3/khertz_count(9)));

FDCPE_u3/khertz_en: FDCPE port map (u3/khertz_en,u3/khertz_en_D,clk,'0','0','1');
     u3/khertz_en_D <= (NOT u3/khertz_count(0) AND NOT u3/khertz_count(1) AND
      u3/mhertz_en AND NOT u3/khertz_count(2) AND u3/khertz_count(3) AND
      NOT u3/khertz_count(4) AND u3/khertz_count(5) AND u3/khertz_count(6) AND
      u3/khertz_count(7) AND u3/khertz_count(8) AND u3/khertz_count(9));

FTCPE_u3/mhertz_count: FTCPE port map (u3/mhertz_count,'0',clk,'0','0','1');

FDCPE_u3/mhertz_en: FDCPE port map (u3/mhertz_en,u3/mhertz_count,clk,'0','0','1');

u4/XLXI_22/S1_or00006 <= (rx_out(7) AND NOT N_PZ_624 AND NOT u4/XLXN_83 AND
NOT u4/XLXI_47/S0_or000011 AND NOT N_PZ_666 AND u4/XLXN_94 AND NOT u4/XLXN_41);

u4/XLXI_46/S1_or00007 <= ((rx_out(7) AND N_PZ_624)
      OR (rx_out(6) AND NOT rx_out(7) AND rx_out(5) AND NOT N_PZ_624)
      OR (rx_out(6) AND NOT rx_out(7) AND NOT N_PZ_624 AND NOT N_PZ_615)
      OR (rx_out(6) AND NOT rx_out(7) AND NOT N_PZ_624 AND
      Mmult_bin_deg_mult0000_Mxor__index0033 AND NOT N_PZ_604)
      OR (rx_out(6) AND rx_out(5) AND NOT N_PZ_624 AND
      NOT Mmult_bin_deg_mult0000__or0031 AND NOT N_PZ_615)
      OR (rx_out(6) AND rx_out(5) AND NOT N_PZ_624 AND NOT N_PZ_615 AND
      NOT N_PZ_604));

u4/XLXI_47/S0_or000011 <= (rx_out(7) AND NOT N_PZ_624 AND NOT u4/XLXN_83 AND N_PZ_666 AND
u4/XLXN_94);

u4/XLXN_27 <= ((bin_deg(4) AND u4/XLXN_83 AND N_PZ_604 AND
      NOT u4/XLXI_46/S1_or00007 AND NOT u4/XLXN_81)
      OR (bin_deg(4) AND NOT u4/XLXN_83 AND NOT N_PZ_604 AND
      u4/XLXI_46/S1_or00007 AND NOT u4/XLXN_81)
      OR (NOT bin_deg(4) AND NOT u4/XLXN_83 AND N_PZ_604 AND
      u4/XLXI_46/S1_or00007 AND u4/XLXN_81)
      OR (NOT bin_deg(4) AND NOT u4/XLXN_83 AND NOT N_PZ_604 AND
      NOT u4/XLXI_46/S1_or00007 AND u4/XLXN_81));

u4/XLXN_28 <= ((u4/XLXN_27)
      OR (u4/XLXN_83 AND NOT N_PZ_666)
      OR (N_PZ_604 AND u4/XLXI_46/S1_or00007)
      OR (NOT bin_deg(4) AND NOT N_PZ_666 AND u4/XLXN_81)
      OR (NOT N_PZ_604 AND NOT N_PZ_666 AND NOT u4/XLXI_46/S1_or00007)
      OR (NOT bin_deg(4) AND u4/XLXN_83 AND NOT N_PZ_604 AND N_PZ_666));

u4/XLXN_29 <= ((NOT bin_deg(4) AND NOT u4/XLXN_94)
      OR (bin_deg(4) AND u4/XLXN_83 AND NOT N_PZ_666 AND NOT u4/XLXN_27)
      OR (bin_deg(4) AND NOT u4/XLXN_83 AND NOT u4/XLXN_81 AND
      NOT u4/XLXN_27)
      OR (bin_deg(4) AND NOT u4/XLXN_83 AND NOT N_PZ_604 AND N_PZ_666 AND
      NOT u4/XLXN_27));

u4/XLXN_33 <= ((N_PZ_606 AND NOT N_PZ_641)
OR (NOT N_PZ_606 AND N_PZ_641));

u4/XLXN_34 <= ((NOT bin_deg(3) AND N_PZ_606 AND u4/XLXN_41)
      OR (bin_deg(3) AND N_PZ_606 AND NOT u4/XLXN_27 AND u4/XLXN_28)
      OR (bin_deg(3) AND NOT N_PZ_606 AND u4/XLXN_28 AND NOT u4/XLXN_29)
      OR (NOT bin_deg(3) AND NOT u4/XLXN_27 AND NOT u4/XLXN_28 AND
      NOT u4/XLXN_35));

u4/XLXN_35 <= ((bin_deg(3) AND N_PZ_606 AND u4/XLXN_27 AND u4/XLXN_28 AND
      NOT u4/XLXN_29)
      OR (bin_deg(3) AND NOT N_PZ_606 AND NOT u4/XLXN_27 AND NOT u4/XLXN_28 AND
      u4/XLXN_29)
      OR (NOT bin_deg(3) AND N_PZ_606 AND NOT u4/XLXN_27 AND NOT u4/XLXN_28 AND
      NOT u4/XLXN_29)
      OR (NOT bin_deg(3) AND NOT N_PZ_606 AND NOT u4/XLXN_27 AND u4/XLXN_28 AND
      u4/XLXN_29));

u4/XLXN_36 <= ((NOT u4/XLXI_47/S0_or000011 AND N_PZ_666 AND NOT u4/XLXN_41 AND
      N_PZ_1022)
      OR (rx_out(7) AND NOT N_PZ_624 AND NOT u4/XLXN_83 AND
      NOT u4/XLXI_47/S0_or000011 AND NOT N_PZ_666 AND u4/XLXN_94 AND u4/XLXN_41 AND N_PZ_1022));

u4/XLXN_37 <= ((NOT u4/XLXI_47/S0_or000011 AND N_PZ_1022 AND
NOT u4/XLXI_22/S1_or00006)
OR (N_PZ_666 AND NOT u4/XLXN_41 AND NOT N_PZ_1022));

u4/XLXN_38 <= ((u4/XLXN_36 AND u4/XLXN_37)
      OR (u4/XLXI_47/S0_or000011 AND NOT u4/XLXN_41 AND
      NOT u4/XLXI_22/S1_or00006)
      OR (NOT u4/XLXI_47/S0_or000011 AND N_PZ_666 AND u4/XLXN_41)
      OR (NOT N_PZ_666 AND NOT u4/XLXN_41 AND NOT u4/XLXI_22/S1_or00006)
      OR (rx_out(7) AND NOT N_PZ_624 AND NOT u4/XLXN_83 AND NOT N_PZ_666 AND
      u4/XLXN_94 AND NOT u4/XLXI_22/S1_or00006));

u4/XLXN_41 <= ((bin_deg(3) AND NOT u4/XLXN_27 AND NOT u4/XLXN_28)
OR (u4/XLXN_27 AND u4/XLXN_28 AND NOT u4/XLXN_29)
OR (NOT u4/XLXN_27 AND NOT u4/XLXN_28 AND u4/XLXN_29));

u4/XLXN_81 <= ((rx_out(7) AND N_PZ_624)
      OR (NOT rx_out(7) AND rx_out(5) AND NOT N_PZ_604)
      OR (rx_out(6) AND rx_out(5) AND N_PZ_615 AND NOT N_PZ_604)
      OR (NOT rx_out(6) AND NOT rx_out(7) AND
      NOT Mmult_bin_deg_mult0000__or0031 AND Mmult_bin_deg_mult0000_Mxor__index0033)
      OR (NOT rx_out(7) AND NOT Mmult_bin_deg_mult0000__or0031 AND
      Mmult_bin_deg_mult0000_Mxor__index0033 AND NOT N_PZ_615)
      OR (rx_out(6) AND rx_out(7) AND rx_out(5) AND NOT N_PZ_615 AND
      NOT u4/XLXI_46/S1_or00007)
      OR (rx_out(6) AND NOT rx_out(7) AND NOT rx_out(5) AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0033 AND N_PZ_615)
      OR (rx_out(6) AND NOT rx_out(7) AND
      Mmult_bin_deg_mult0000_Mxor__index0033 AND N_PZ_615 AND N_PZ_604)
      OR (rx_out(6) AND NOT N_PZ_624 AND
      NOT Mmult_bin_deg_mult0000__or0031 AND Mmult_bin_deg_mult0000_Mxor__index0033 AND
      NOT u4/XLXI_46/S1_or00007));

u4/XLXN_83 <= ((NOT rx_out(6) AND rx_out(7) AND NOT rx_out(5) AND NOT N_PZ_624 AND
      NOT N_PZ_653)
      OR (NOT rx_out(6) AND rx_out(7) AND NOT rx_out(5) AND
      NOT Mmult_bin_deg_mult0000_Mxor__index0033 AND N_PZ_653)
      OR (NOT rx_out(6) AND rx_out(7) AND NOT N_PZ_624 AND
      Mmult_bin_deg_mult0000__or0031 AND N_PZ_604));

u4/XLXN_94 <= ((NOT bin_deg(4) AND u4/XLXN_27)
      OR (u4/XLXN_83 AND NOT N_PZ_666)
      OR (NOT u4/XLXN_83 AND N_PZ_666 AND NOT u4/XLXN_81)
      OR (NOT N_PZ_604 AND N_PZ_666 AND u4/XLXN_81)
      OR (NOT N_PZ_666 AND NOT u4/XLXI_46/S1_or00007 AND NOT u4/XLXN_81));

Register Legend:
      FDCPE (Q,D,C,CLR,PRE,CE);
      FDDCPE (Q,D,C,CLR,PRE,CE);
      FTCPE (Q,D,C,CLR,PRE,CE);
      FTDCPE (Q,D,C,CLR,PRE,CE);
      LDCP (Q,D,G,CLR,PRE);